Semiconductor device with a field plate trench having a thick bottom dielectric

• US 9,299,793 B2
• Filed: 05/01/2014
• Issued: 03/29/2016
• Est. Priority Date: 05/16/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Inventors: Henson, Timothy D., Kelkar, Kapil, Radic, Ljubo
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US14/267,760
• Publication Number:
  US 20140339669A1
• Time in Patent Office: 698 Days
• Field of Search: 438/259, 438/270, 438/271, 438/589, 257/328, 257/330, 257/341
• US Class Current: 1/1
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Disclosed is a power device, such as a power MOSFET, and methods for fabricating same. The device includes a field plate trench. The device further includes first and second trench dielectrics inside the field plate trench. The device also includes a field plate situated over the first trench dielectric and within the second trench dielectric. A combined thickness of the first and second trench dielectrics at a bottom of the field plate trench is greater than a sidewall thickness of the second trench dielectric.

Claims

1. A power semiconductor device comprising:

a field plate trench;

a first trench dielectric situated in and contacting a bottom of said field plate trench;

a second trench dielectric situated over said first trench dielectric and directly contacting sidewalls of said field plate trench;

a field plate situated over said first trench dielectric and within said second trench dielectric;

a combined thickness of said first and second trench dielectrics at said bottom of said field plate trench being greater than a sidewall thickness of said second trench dielectric.

2. The power semiconductor device of claim 1, wherein said first trench dielectric is thermally grown in said field plate trench and said second trench dielectric is deposited in said field plate trench.

3. The power semiconductor device of claim 1, wherein said first trench dielectric is deposited in said field plate trench and said second trench dielectric is thermally grown in said field plate trench.

4. The power semiconductor device of claim 1, wherein a first dielectric material used in said first trench dielectric is different from a second dielectric material used in said second trench dielectric.

5. The power semiconductor device of claim 1, wherein said sidewalls of said field plate trench are at an angle of no less than 80 degrees and no more than 90 degrees with respect to a bottom surface of said power semiconductor device.

6. The power semiconductor device of claim 1, wherein said combined thickness is at least 120% greater than said sidewall thickness.

7. The power semiconductor device of claim 1, wherein said first trench dielectric completely fills said bottom of said field plate trench.

8. A method of fabricating a power semiconductor device, said method comprising:

forming a field plate trench in a semiconductor substrate;

forming a first trench dielectric;

forming a sacrificial mask within said first trench dielectric;

etching said first trench dielectric situated on said sidewalls to a depth;

removing said sacrificial mask;

depositing a second trench dielectric over said first trench dielectric, such that a combined thickness of said first and second trench dielectrics at a bottom of said field plate trench is greater than a sidewall thickness of said second trench dielectric;

forming a field plate in said field plate trench.

9. The method of claim 8, wherein said forming said sacrificial mask comprises:

depositing a sacrificial mask material into said field plate trench;

etching said sacrificial mask material.

10. The method of claim 8, wherein said forming said first trench dielectric includes thermally growing said first trench dielectric in said field plate trench.

11. The method of claim 8, wherein said forming said first trench dielectric includes depositing said first trench dielectric in said field plate trench.

12. The method of claim 8, wherein said forming said second trench dielectric includes depositing said second trench dielectric in said field plate trench.

13. The method of claim 8, wherein said combined thickness is at least 120% greater than said sidewall thickness.

14. A method of fabricating a power semiconductor device, said method comprising:

forming a field plate trench;

forming a first trench dielectric in and contacting a bottom of said field plate trench;

partially etching said first trench dielectric on sidewalls of said field plate trench;

forming a second trench dielectric over said first trench dielectric and directly contacting said sidewalls of said field plate trench without filling said field plate trench;

forming a field plate in said field plate trench;

wherein a combined thickness of said first and second trench dielectrics at a bottom of said field plate trench is greater than a sidewall thickness of said second trench dielectric.

15. The method of claim 14, wherein said forming said first trench dielectric includes depositing said first trench dielectric in said field plate trench.

16. The method of claim 15, wherein said depositing said first trench dielectric completely fills said field plate trench.

17. The method of claim 15, wherein said depositing said first trench dielectric partially fills said field plate trench.

18. The method of claim 14, wherein said forming said second trench dielectric includes depositing said second trench dielectric in said field plate trench.

19. The method of claim 14, wherein said forming said second trench dielectric includes thermally growing said second trench dielectric in said field plate trench.

20. The method of claim 14, wherein said combined thickness is at least 120% greater than said sidewall thickness.