Method for fabricating a transistor device with a tuned dopant profile

• US 9,299,801 B1
• Filed: 03/14/2013
• Issued: 03/29/2016
• Est. Priority Date: 03/14/2013
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Bakhishev, Teymur, Pradhan, Sameer, Hoffmann, Thomas, Sonkusale, Sachin R.
• Primary Examiner(s): Payen, Marvin
• Application Number:
  US13/828,262
• Time in Patent Office: 1,111 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66568 Lateral single gate silicon transistors
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. Different transistor devices with similar boron implants may be fabricated with different peak locations and heights for their respective dopant profiles by tailoring the carbon implant energy to effect tuned dopant profiles for the boron.

Claims

1. A method for fabricating a transistor device having a gate, a channel, a source and a drain on either side of the channel, the channel having a tuned dopant profile, comprising:

defining an implant region;

performing a first implantation of a first dopant migration mitigating material into the implant region at a first preselected dopant migration mitigating energy and dose;

implanting a screening layer into the implant region at a preselected screening layer energy and screening layer dose, the screening layer defining a depletion width for the transistor channel when a voltage is applied to the gate;

implanting a threshold voltage set layer into the implant region at a preselected threshold voltage set layer energy and threshold voltage set layer dose;

wherein the first preselected dopant migration mitigating energy effects the placement of a peak of a dopant profile of the screening layer at a first location and a first thickness;

wherein the preselected threshold voltage set layer energy and threshold voltage set layer dose effects the placement of the peak of a dopant profile of the threshold voltage layer to be different from the first location;

wherein the threshold voltage set layer is coextensive with the screening layer and abuts the source and drain and the screening layer extends laterally across the channel.

2. The method of claim 1, further including the step of performing a second implantation of a second dopant mitigating material at a second preselected dopant mitigating material energy and dose.

3. The method of claim 2, wherein the first implantation of a dopant migration mitigating material is implanted at a first energy and the second implantation of a dopant migration mitigating material is implanted at a second energy, the first energy being lower than the second energy.

4. The method of claim 2, wherein both the first dopant migration mitigating material and second dopant migration mitigating material comprise carbon.

5. The method of claim 4, wherein the first implantation is at a first energy, and the second implantation is at a second energy, the second energy being higher than the first energy.

6. The method of claim 1, wherein the first and second energies for the first and second dopant migration mitigating material implantations are identical.

7. The method of claim 1, wherein the first dopant migration mitigating material comprises carbon.

8. The method of claim 1, further comprising:

creating a narrower peak profile for the screening layer compared with the threshold voltage set layer.

9. The method of claim 1, further comprising:

implanting an anti-punchthrough layer into the implant region.

10. The method of claim 1, further comprising:

forming an undoped channel layer on the implant region.

11. A method for fabricating transistor devices with tuned dopant profiles, comprising:

providing a first implant region for a first transistor device;

performing a first implantation of a carbon material into the first implant region;

performing a second implantation of a carbon material into the first implant region;

implanting a first screening layer into the first implant region;

providing a second implant region for a second transistor device;

implanting a second screening layer into the second implant region;

wherein process conditions for implanting the first implantation of a carbon material and the second implantation of a carbon material and the first screening layer are selected to effect a location of a peak and thickness of a dopant profile of the first screening layer;

wherein process conditions for implanting a second screening layer are selected to effect a location of a peak and thickness of a dopant profile of the second screening layer.

12. The method of claim 11, further including the step of implanting a first threshold voltage layer into the first implant region.

13. The method of claim 11, further including the step of implanting a second threshold voltage layer into the second implant region.

14. The method of claim 11, further comprising:

selecting a lower energy for the first implantation and a higher energy for the second implantation, resulting in a narrower peak profile for the first screening layer as a result of the selection of the lower energy for the first implantation.