Semiconductor device and driving method thereof

• US 9,299,813 B2
• Filed: 11/25/2014
• Issued: 03/29/2016
• Est. Priority Date: 08/06/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Inoue, Hiroki, Kato, Kiyoshi, Matsuzaki, Takanori, Nagatsuka, Shuhei
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US14/552,551
• Publication Number:
  US 20150155289A1
• Time in Patent Office: 490 Days
• Field of Search: 365/149, 365/185.1, 365/185.14, 365/185.26
• US Class Current: 1/1
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 16/0408 comprising cells containing floating gate transistors G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/425 producing ion implantation
• CPC Class Codes: H01L 21/441 Deposition of conductive or insulating materials for electrodes
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78651 Silicon transistors H01L29/78606 - H01L29/78645 take precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 41/40 : characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/70 : the floating gate being an electrode shared by two or more components
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

Claims

1. A semiconductor device comprising:

a bit line;

a source line;

a word line; and

a memory cell comprising a first transistor and a second transistor,

wherein the first transistor is a p-channel transistor,

wherein the first transistor comprises a first gate, a first source, a first drain, and a first channel formation region comprising crystalline silicon,

wherein the second transistor comprises a second gate, a second source, a second drain, and an oxide semiconductor layer including a second channel formation region,

wherein the first gate is electrically connected to one of the second source and the second drain,

wherein one of the first source and the first drain and the other of the second source and the second drain are electrically connected to the bit line,

wherein the other of the first source and the first drain is electrically connected to the source line, and

wherein the second gate is electrically connected to the word line.

2. The semiconductor device according to claim 1, wherein the second transistor overlaps with the first transistor with a first insulating layer interposed therebetween.

3. The semiconductor device according to claim 2, further comprising a second insulating layer covering the second transistor,

wherein the bit line is over the second insulating layer.

4. The semiconductor device according to claim 1, wherein the second transistor is an n-channel transistor.

5. The semiconductor device according to claim 1, further comprising a source line switching circuit electrically connected to the source line,

wherein the source line switching circuit is configured to switch a potential of the source line.

6. The semiconductor device according to claim 5, further comprising a first driver circuit, a second driver circuit and a third driver circuit,

wherein the bit line is electrically connected to the first driver circuit,

wherein the word line is electrically connected to the second driver circuit, and

wherein the third driver circuit is configured to control the source line switching circuit, the first driver circuit and the second driver circuit.

7. A semiconductor device comprising:

a bit line;

a source line;

a first word line;

a second word line; and

a memory cell comprising a first transistor, a second transistor and a capacitor,

wherein the first transistor is a p-channel transistor,

wherein the first transistor comprises a first gate, a first source, a first drain, and a first channel formation region comprising crystalline silicon,

wherein the second transistor comprises a second gate, a second source, a second drain, and an oxide semiconductor layer including a second channel formation region,

wherein the first gate, one of the second source and the second drain, and one of a pair of electrodes of the capacitor are electrically connected to one another,

wherein one of the first source and the first drain and the other of the second source and the second drain are electrically connected to the bit line,

wherein the other of the first source and the first drain is electrically connected to the source line,

wherein the second gate is electrically connected to the first word line, and

wherein the other of the pair of electrodes of the capacitor is electrically connected to the second word line.

8. The semiconductor device according to claim 7, wherein the capacitor and the second transistor overlap with the first transistor with a first insulating layer interposed therebetween.

9. The semiconductor device according to claim 8, further comprising a second insulating layer covering the second transistor,

wherein the bit line is over the second insulating layer.

10. The semiconductor device according to claim 7, wherein the second transistor is an n-channel transistor.

11. The semiconductor device according to claim 7, further comprising a source line switching circuit electrically connected to the source line,

wherein the source line switching circuit is configured to switch a potential of the source line.

12. The semiconductor device according to claim 11, further comprising a first driver circuit, a second driver circuit and a third driver circuit,

wherein the bit line is electrically connected to the first driver circuit,

wherein the first word line and the second word line are electrically connected to the second driver circuit, and

wherein the third driver circuit is configured to control the source line switching circuit, the first driver circuit and the second driver circuit.

13. A semiconductor device comprising:

a bit line;

a first word line;

a second word line;

a first memory cell and a second memory cell, each of the first memory cell and the second memory cell comprising;

a first transistor; and

a second transistor,

wherein the first transistor is a p-channel transistor,

wherein the first transistor comprises a first gate, a first source, a first drain, and a first channel formation region comprising crystalline silicon,

wherein the second transistor comprises a second gate, a second source, a second drain, and an oxide semiconductor layer including a second channel formation region, and

wherein the first gate is electrically connected to one of the second source and the second drain,

wherein one of the first source and the first drain and the other of the second source and the second drain in each of the first memory cell and the second memory cell are electrically connected to the bit line,

wherein the second gate in the first memory cell is electrically connected to the first word line, and

wherein the second gate in the second memory cell is electrically connected to the second word line.

14. The semiconductor device according to claim 13,

wherein each of the first memory cell and the second memory cell further comprises a capacitor, and

wherein one of a pair of electrodes of the capacitor is electrically connected to the first gate.

15. The semiconductor device according to claim 13, wherein in each of the first memory cell and the second memory cell, the second transistor overlaps with the first transistor with a first insulating layer interposed therebetween.

16. The semiconductor device according to claim 15, further comprising a second insulating layer covering the second transistor in each of the first memory cell and the second memory cell,

wherein the bit line is over the second insulating layer.

17. The semiconductor device according to claim 13, wherein the second transistor is an n-channel transistor.

18. The semiconductor device according to claim 13, further comprising a source line and a source line switching circuit electrically connected to the source line,

wherein the source line is electrically connected to the other of the second source and the second drain in each of the first memory cell and the second memory cell, and

wherein the source line switching circuit is configured to switch a potential of the source line.

19. The semiconductor device according to claim 18, further comprising a first driver circuit, a second driver circuit and a third driver circuit,

wherein the bit line is electrically connected to the first driver circuit,

wherein the first word line and the second word line are electrically connected to the second driver circuit, and

wherein the third driver circuit is configured to control the source line switching circuit, the first driver circuit and the second driver circuit.