Semiconductor device and driving method thereof
First Claim
1. A semiconductor device comprising:
- a bit line;
a source line;
a word line; and
a memory cell comprising a first transistor and a second transistor,wherein the first transistor is a p-channel transistor,wherein the first transistor comprises a first gate, a first source, a first drain, and a first channel formation region comprising crystalline silicon,wherein the second transistor comprises a second gate, a second source, a second drain, and an oxide semiconductor layer including a second channel formation region,wherein the first gate is electrically connected to one of the second source and the second drain,wherein one of the first source and the first drain and the other of the second source and the second drain are electrically connected to the bit line,wherein the other of the first source and the first drain is electrically connected to the source line, andwherein the second gate is electrically connected to the word line.
1 Assignment
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Accused Products
Abstract
A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.
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Citations
19 Claims
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1. A semiconductor device comprising:
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a bit line; a source line; a word line; and a memory cell comprising a first transistor and a second transistor, wherein the first transistor is a p-channel transistor, wherein the first transistor comprises a first gate, a first source, a first drain, and a first channel formation region comprising crystalline silicon, wherein the second transistor comprises a second gate, a second source, a second drain, and an oxide semiconductor layer including a second channel formation region, wherein the first gate is electrically connected to one of the second source and the second drain, wherein one of the first source and the first drain and the other of the second source and the second drain are electrically connected to the bit line, wherein the other of the first source and the first drain is electrically connected to the source line, and wherein the second gate is electrically connected to the word line. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor device comprising:
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a bit line; a source line; a first word line; a second word line; and a memory cell comprising a first transistor, a second transistor and a capacitor, wherein the first transistor is a p-channel transistor, wherein the first transistor comprises a first gate, a first source, a first drain, and a first channel formation region comprising crystalline silicon, wherein the second transistor comprises a second gate, a second source, a second drain, and an oxide semiconductor layer including a second channel formation region, wherein the first gate, one of the second source and the second drain, and one of a pair of electrodes of the capacitor are electrically connected to one another, wherein one of the first source and the first drain and the other of the second source and the second drain are electrically connected to the bit line, wherein the other of the first source and the first drain is electrically connected to the source line, wherein the second gate is electrically connected to the first word line, and wherein the other of the pair of electrodes of the capacitor is electrically connected to the second word line. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A semiconductor device comprising:
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a bit line; a first word line; a second word line; a first memory cell and a second memory cell, each of the first memory cell and the second memory cell comprising; a first transistor; and a second transistor, wherein the first transistor is a p-channel transistor, wherein the first transistor comprises a first gate, a first source, a first drain, and a first channel formation region comprising crystalline silicon, wherein the second transistor comprises a second gate, a second source, a second drain, and an oxide semiconductor layer including a second channel formation region, and wherein the first gate is electrically connected to one of the second source and the second drain, wherein one of the first source and the first drain and the other of the second source and the second drain in each of the first memory cell and the second memory cell are electrically connected to the bit line, wherein the second gate in the first memory cell is electrically connected to the first word line, and wherein the second gate in the second memory cell is electrically connected to the second word line. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification