Insulating gate-type bipolar transistor

• US 9,299,818 B2
• Filed: 05/29/2012
• Issued: 03/29/2016
• Est. Priority Date: 05/29/2012
• Status: Active Grant

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Aono, Shinji, Minato, Tadaharu
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US14/395,914
• Publication Number:
  US 20150129930A1
• Time in Patent Office: 1,400 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

An object of the present invention is to provide a trench gate type IGBT achieving both retention of withstand voltage and lowering of ON-state voltage and to provide a method for manufacturing the trench gate type IGBT. The IGBT according to the present invention is an SJ-RC-IGBT which includes a drift layer having super junction structure, and includes an IGBT area and an FWD area on the rear surface. In the IGBT according to the present invention, a first drift layer has an impurity concentration of 1×10¹⁵ atms/cm³ or higher and lower than 2×10¹⁶ atms/cm³, and a thickness of 10 μm or larger and smaller than 50 μm; and that a buffer layer has an impurity concentration of 1×10¹⁵ atms/cm³ or higher and lower than 2×10¹⁶ atms/cm³, and a thickness of 2 μm or larger and smaller than 15 μm.

Claims

1. An insulating gate-type bipolar transistor comprising:

a first conductivity-type buffer layer;

a first drift layer provided on a first main surface of said buffer layer;

a first conductivity-type second drift layer provided on said first drift layer;

a second conductivity-type base layer provided on said second drift layer;

a first conductivity-type emitter layer selectively provided on the front surface of said base layer;

a gate electrode penetrating from the front surface of said emitter layer into said second drift layer to be embedded with an insulating gate film interposed between the gate electrode and the surroundings;

an emitter electrode having conductivity with said emitter layer;

a collector layer provided on a second main surface of said buffer layer; and

a collector electrode provided on said collector layer,

wherein

said first drift layer has a structure containing first conductivity-type first layers and second conductivity-type second layers repeated in the horizontal direction,

said collector layer has a structure containing second conductivity-type first collector layers and first conductivity-type second collector layers repeated in the horizontal direction,

said first drift layer has an impurity concentration of 1×

10¹⁵ atoms/cm³ or higher and lower than 2×

10¹⁶ atoms/cm³, and a thickness of 10 μ

m or larger and smaller than 50 μ

m, and

said buffer layer has an impurity concentration of 1×

10¹⁵ atoms/cm³ or higher and lower than 2×

10¹⁶ atoms/cm³, and a thickness of 2 μ

m or larger and smaller than 15 μ

m.

2. The insulating gate-type bipolar transistor according to claim 1, wherein insulating layers are appropriately provided between said first layers and said second layers.

3. The insulating gate-type bipolar transistor according to claim 1, further comprising

a first conductivity-type carrier accumulating layer having a higher impurity concentration than the impurity concentration of said second drift layer between said second drift layer and said base layer in a condition in contact with said base layer.

4. The insulating gate-type bipolar transistor according to claim 1, wherein the repetition pitch of said collector layer is equal to or longer than 5 times longer than the repetition pitch of said first drift layer, and shorter than 20000 times longer than the repetition pitch of said first drift layer.

5. The insulating gate-type bipolar transistor according to claim 1, wherein the width of said second conductivity-type collector layers is determined such that voltage drop of 0.5 V or higher and lower than 0.7 V is generated in said buffer layer between intermediate positions of said first collector layers and said second collector layers at the current density at the time of snapback peak voltage.

6. An insulating gate-type bipolar transistor comprising:

a first conductivity-type buffer layer;

a first drift layer provided on a first main surface of said buffer layer;

a first conductivity-type second drift layer provided on said first drift layer;

a second conductivity-type base layer provided on said second drift layer;

a first conductivity-type emitter layer selectively provided on the front surface of said base layer;

a gate electrode penetrating from the front surface of said emitter layer into said second drift layer to be embedded with an insulating gate film interposed between the gate electrode and the surroundings;

an emitter electrode having conductivity with said emitter layer;

a collector layer provided on a second main surface of said buffer layer; and

a collector electrode provided on said collector layer,

wherein

said first drift layer has a structure containing first conductivity-type first layers, insulating layers, and second conductivity-type second layers repeated in this order in the horizontal direction,

said collector layer has a structure containing second conductivity-type first collector layers and first conductivity-type second collector layers repeated in the horizontal direction,

said first layers and said second layers have an impurity concentration of 1×

10¹⁵ atoms/cm³ or higher and lower than 2×

10¹⁶ atoms/cm³,

said first drift layer has a thickness of 10 μ

m or larger and smaller than 50 μ

m, and

said buffer layer has an impurity concentration of 1×

10¹⁵ atoms/cm³ or higher and lower than 2×

10¹⁶ atoms/cm³, and a thickness of 2 μ

m or larger and smaller than 15 μ

m.

7. The insulating gate-type bipolar transistor according to claim 6, further comprising

a first conductivity-type carrier accumulating layer having a higher impurity concentration than the impurity concentration of said second drift layer between said second drift layer and said base layer in a condition in contact with said base layer.

8. The insulating gate-type bipolar transistor according to claim 6, wherein the repetition pitch of said collector layer is equal to or longer than 5 times longer than the repetition pitch of said first drift layer, and shorter than 20000 times longer than the repetition pitch of said first drift layer.

9. The insulating gate-type bipolar transistor according to claim 6, wherein the width of said second conductivity-type collector layers is determined such that voltage drop of 0.5 V or higher and lower than 0.7 V is generated in said buffer layer between intermediate positions of said first collector layers and said second collector layers at the current density at the time of snapback peak voltage.