Semiconductor integrated circuit devices including gates having connection lines thereon

• US 9,299,827 B2
• Filed: 10/16/2014
• Issued: 03/29/2016
• Est. Priority Date: 02/21/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Bong-Soo, Shin, Soo-Ho, Hong, Hyeong-Sun, Ryu, Ho-In
• Primary Examiner(s): SANDVIK, BENJAMIN P
• Application Number:
  US14/516,201
• Publication Number:
  US 20150035025A1
• Time in Patent Office: 530 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

Provided are semiconductor integrated circuit (IC) devices including gate patterns having a step difference therebetween and a connection line interposed between the gate patterns. The semiconductor IC device includes a semiconductor substrate including a peripheral active region, a cell active region, and a device isolation layer. Cell gate patterns are disposed on the cell active region and the device isolation layer. A peripheral gate pattern is disposed on the peripheral active region. A cell electrical node is disposed on the cell active region adjacent to the cell gate patterns. Peripheral electrical nodes are disposed on the peripheral active region adjacent to the peripheral gate pattern. Connection lines are disposed on the cell gate patterns disposed on the device isolation layer. The connection lines are connected between the cell gate patterns and the peripheral gate pattern.

Claims

1. A semiconductor device comprising:

a semiconductor substrate comprising a cell array region including a cell central region and a cell edge region, and a peripheral circuit region;

cell gate patterns extending from the cell central region to the cell edge region, each comprising a cell gate capping pattern on a cell gate in the cell central region, wherein an upper surface of a cell gate in the cell edge region is beneath a surface of a device isolation layer;

an interlayer insulating layer on the cell edge region and on the peripheral circuit region, having a contact hole extending therethrough into the device isolation layer in the cell edge region, exposing a portion of the upper surface of the cell gate in the cell edge region; and

a conductive layer in the contact hole extending through the interlayer insulating layer and into the device isolation layer to contact an entire width of the portion of the upper surface of the cell gate in the cell edge region, and wherein the conductive layer contacts the device isolation layer.

2. The device of claim 1, wherein the interlayer insulating layer is planar extending from the cell edge region to the peripheral circuit region.

3. The device of claim 1, further comprising:

a peripheral gate pattern on an active region in the peripheral circuit region and on first and second peripheral impurity diffusion regions in the active region;

a first peripheral electrical node extending through the interlayer insulating layer to contact one of the first and second peripheral impurity diffusion regions, wherein the first peripheral electrical node and the conductive layer comprise a common layer.

4. The device of claim 3, wherein the peripheral gate pattern comprises a peripheral gate lower pattern, a peripheral gate upper pattern, and a peripheral gate capping pattern;

and

wherein an upper surface of the peripheral gate lower pattern and an upper surface of the cell gate capping pattern are at equal heights.

5. The device of claim 3, wherein the interlayer insulating layer extends to the cell central region, the device further comprising:

first and second cell array transistors in the cell central region, beneath the interlayer insulating layer, including the cell gate patterns and associated cell impurity diffusion regions to provide a common cell impurity diffusion region for the first and second cell array transistors; and

a bit line structure, extending through the interlayer insulating layer to contact the common cell impurity diffusion region.

6. The device of claim 5, wherein the bit line structure comprises the common layer.

7. The device of claim 1, wherein the cell gate capping patterns protrude from an uppermost surface of the substrate.

8. The device of claim 1, wherein the device isolation layer in the cell edge region extends to the peripheral circuit region and defines a first active region in the cell central region and a second active region in the peripheral circuit region.

9. The device of claim 1, wherein the contact hole exposes an entire width of the upper surface of the cell gate pattern in the cell edge region.

10. The device of claim 9, wherein the conductive layer is in contact with the entire width of the upper surface of the cell gate pattern in the cell edge region.

11. A semiconductor device comprising:

a semiconductor substrate comprising a cell array region including a cell central region and a cell edge region, and a peripheral circuit region;

first and second directly adjacent cell gate patterns on the semiconductor substrate, each comprising a cell gate capping pattern on a cell gate in the cell central region, extending from the cell central region to the cell edge region, wherein portions of upper surfaces of the cell gates in the cell edge region are free of the cell gate capping pattern to provide first and second exposed upper surfaces of the cell gates beneath a surface of a device isolation layer in the cell edge region;

an interlayer insulating layer on the cell central region, the cell edge region and on the peripheral circuit region;

a first conductive layer extending through the interlayer insulating layer into the device isolation layer to contact an entire width of the first exposed upper surface on a first side of the cell central region and the device isolation layer; and

a second conductive layer extending through the interlayer insulating layer into the device isolation layer to contact an entire width of the second exposed upper surface on a second side of the cell central region and the device isolation layer, opposite the first side.

12. The device of claim 11 further comprising:

first and second cell array transistors in the cell central region, including the first and second directly adjacent cell gate patterns, respectively, and associated cell impurity diffusion regions to provide a common cell impurity diffusion region for the first and second cell array transistors between the first and second directly adjacent cell gate patterns.

13. The device of claim 11 further comprising:

an active region in the cell array region, wherein the first and second directly adjacent cell gate patterns cross over the active region to form acute angles relative to a boundary of the active region.

14. A random access memory device comprising:

a semiconductor substrate comprising a cell array region including a cell central region and a cell edge region, and a peripheral circuit region substantially surrounding the cell array region;

a cell gate pattern on the substrate, extending from the cell central region to the cell edge region, the cell gate pattern comprising a cell gate capping pattern on a cell gate beneath a surface of an active region in the cell central region, wherein a portion of an upper surface of the cell gate in the cell edge region is free of the cell gate capping pattern to expose an entire width of the upper surface of the portion beneath a surface of a device isolation layer in the cell edge region;

a cell array transistor in the cell central region, including the cell gate pattern, and associated cell impurity diffusion regions;

an interlayer insulating layer on the cell central region, the cell edge region and the peripheral circuit region; and

a conductive layer extending through the interlayer insulating layer to contact the entire width of the exposed upper surface of the cell gate in the cell edge region.

15. The device of claim 14 further comprising:

a bit line pattern, extending through the interlayer insulating layer to contact a first of the associated cell impurity diffusion regions.

16. The device of claim 15, wherein the interlayer insulating layer comprises a first interlayer insulating layer, the device further comprising:

a second interlayer insulating layer on the first interlayer insulating layer, wherein an uppermost surface of the bit line pattern is buried in the second interlayer insulating layer; and

an electrical node, extending from a surface of the second interlayer insulating layer through the second interlayer insulating layer and through the first interlayer insulating layer to contact a second of the associated cell impurity diffusion regions.

17. The device of claim 16 further comprising:

a storage structure on the second interlayer insulating layer electrically connected to the electrical node.

18. The device of claim 17, wherein the storage structure comprises a capacitor, a phase-change material, or a ferroelectric material.

19. The device of claim 17 wherein an uppermost level of the conductive layer is located beneath the storage structure.

20. The device of claim 14 further comprising:

a planar transistor in the peripheral circuit region on an upper surface of an active region in the peripheral circuit region.

21. The device of claim 14 wherein the cell gate capping pattern protrudes from a surface of an active region in the cell central region and at least a portion of the cell gate is beneath the surface of the active region in the cell central region.

22. A semiconductor device comprising:

a semiconductor substrate comprising a cell array region including a cell central region and a cell edge region, and a peripheral circuit region;

cell gate patterns extending from the cell central region to the cell edge region, each comprising a cell gate capping pattern on a cell gate in the cell central region, wherein an upper surface of a cell gate in the cell edge region is beneath a surface of a device isolation layer;

an interlayer insulating layer on the cell edge region and on the peripheral circuit region, having a contact hole extending therethrough into the device isolation layer in the cell edge region so that portions of the device isolation layer form side walls of the contact hole, wherein the contact hole exposes a portion of an upper surface of the cell gate in the cell edge region and wherein the contact hole is wider than an entire width of the portion of the cell gate exposed by the contact hole; and

a conductive layer in the contact hole extending through the interlayer insulating layer and into the device isolation layer to contact an entire width of the portion of the upper surface of the cell gate in the cell edge region.

23. A semiconductor device comprising:

a semiconductor substrate comprising a cell array region including a cell central region and a cell edge region, and a peripheral circuit region;

first and second directly adjacent cell gate patterns on the substrate, each comprising a cell gate capping pattern on a cell gate in the cell central region, extending from the cell central region to the cell edge region, wherein entire upper surfaces of cell gates in the cell edge region are free of the cell gate capping pattern to provide first and second exposed upper surfaces of the cell gates in the cell edge region beneath a surface of a device isolation layer in the cell edge region;

an interlayer insulating layer on the cell central region, the cell edge region and on the peripheral circuit region having first and second contact holes extending therethrough into the device isolation layer in the cell edge region so that portions of the device isolation layer form side walls of the first and second contact holes, wherein the first and second contact holes are wider than first and second exposed upper surfaces of the cell gates in the cell edge region, respectively;

a first conductive layer in the first contact hole extending through the interlayer insulating layer into the device isolation layer to contact the first exposed upper surface on a first side of the cell central region; and

a second conductive layer in the second contact hole extending through the interlayer insulating layer into the device isolation layer to contact the second exposed upper surface on a second side of the cell central region, opposite the first side.