Semiconductor device having dual gate insulating layers

• US 9,299,855 B2
• Filed: 07/31/2014
• Issued: 03/29/2016
• Est. Priority Date: 08/09/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Hirohashi, Takuya, Takahashi, Masahiro, Nakashima, Motoki, Watanabe, Ryosuke, Tsubuku, Masashi
• Primary Examiner(s): Soward, Ida M
• Application Number:
  US14/447,875
• Publication Number:
  US 20150041801A1
• Time in Patent Office: 607 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A semiconductor device includes a semiconductor layer, a gate electrode overlapping with the semiconductor layer, a first gate insulating layer between the semiconductor layer and the gate electrode, and a second gate insulating layer between the first gate insulating layer and the gate electrode. The first gate insulating layer includes an oxide in which the nitrogen content is lower than or equal to 5 at. %, and the second gate insulating layer includes charge trap states.

Claims

1. A semiconductor device comprising:

a semiconductor layer;

a gate electrode overlapping with the semiconductor layer;

a first gate insulating layer between the semiconductor layer and the gate electrode; and

a second gate insulating layer between the first gate insulating layer and the gate electrode,

wherein the semiconductor layer includes an oxide semiconductor,

wherein the first gate insulating layer includes an oxide whose nitrogen content is lower than or equal to 5 at. %, and

wherein the second gate insulating layer includes a charge trap state.

2. The semiconductor device according to claim 1,

wherein an electron is trapped in the charge trap state, and

wherein the second gate insulating layer is negatively charged.

3. The semiconductor device according to claim 1, wherein the second gate insulating layer includes hafnium oxide.

4. The semiconductor device according to claim 1, wherein the first gate insulating layer includes silicon oxide.

5. The semiconductor device according to claim 1, wherein the oxide semiconductor is an In—

Ga—

Zn-based oxide.

6. The semiconductor device according to claim 1,

wherein the semiconductor layer includes crystals of the oxide semiconductor,

wherein each c-axis of the crystals is aligned in a direction perpendicular to a surface of the semiconductor layer, and

wherein each of the crystals is a non-single-crystal.

7. The semiconductor device according to claim 1, wherein the gate electrode faces a side surface of the semiconductor layer.

8. The semiconductor device according to claim 1, further comprising:

a source electrode in contact with a side surface of the semiconductor layer; and

a drain electrode in contact with a side surface of the semiconductor layer,

wherein the gate electrode faces a side surface of the semiconductor layer.

9. The semiconductor device according to claim 1, wherein the gate electrode is located over the semiconductor layer.

10. The semiconductor device according to claim 1, wherein the nitrogen content is lower than or equal to 0.1 at. %.

11. A semiconductor device comprising:

a semiconductor layer;

a gate electrode overlapping with the semiconductor layer;

a first gate insulating layer between the semiconductor layer and the gate electrode; and

a second gate insulating layer between the first gate insulating layer and the gate electrode,

wherein the semiconductor layer includes an oxide semiconductor,

wherein the first gate insulating layer includes silicon oxide whose nitrogen content is lower than or equal to 5 at. %, and

wherein the second gate insulating layer includes hafnium oxide and is negatively charged.

12. The semiconductor device according to claim 11, wherein the oxide semiconductor is an In—

Ga—

Zn-based oxide.

13. The semiconductor device according to claim 11,

wherein the semiconductor layer includes crystals of the oxide semiconductor,

wherein each c-axis of the crystals is aligned in a direction perpendicular to a surface of the semiconductor layer, and

wherein each of the crystals is a non-single-crystal.

14. The semiconductor device according to claim 11, wherein the gate electrode faces a side surface of the semiconductor layer.

15. The semiconductor device according to claim 11, further comprising:

a source electrode in contact with a side surface of the semiconductor layer; and

a drain electrode in contact with a side surface of the semiconductor layer,

wherein the gate electrode faces a side surface of the semiconductor layer.

16. The semiconductor device according to claim 11, wherein the gate electrode is located over the semiconductor layer.

17. The semiconductor device according to claim 11, wherein the nitrogen content is lower than or equal to 0.1 at. %.

18. A semiconductor device comprising:

a transistor comprising;

a semiconductor layer;

a gate electrode overlapping with the semiconductor layer;

a first gate insulating layer between the semiconductor layer and the gate electrode; and

a second gate insulating layer between the first gate insulating layer and the gate electrode,

wherein the semiconductor layer includes an oxide semiconductor,

wherein the first gate insulating layer includes silicon oxide whose nitrogen content is lower than or equal to 5 at. %,

wherein the second gate insulating layer includes hafnium oxide, and

wherein a threshold voltage of the transistor is higher than or equal to 0 V.

19. The semiconductor device according to claim 18, wherein the oxide semiconductor is an In—

Ga—

Zn-based oxide.

20. The semiconductor device according to claim 18,

wherein the semiconductor layer includes crystals of the oxide semiconductor,

wherein each c-axis of the crystals is aligned in a direction perpendicular to a surface of the semiconductor layer, and

wherein each of the crystals is a non-single-crystal.

21. The semiconductor device according to claim 18, wherein the gate electrode faces a side surface of the semiconductor layer.

22. The semiconductor device according to claim 18, further comprising:

a source electrode in contact with a side surface of the semiconductor layer; and

a drain electrode in contact with a side surface of the semiconductor layer,

wherein the gate electrode faces a side surface of the semiconductor layer.

23. The semiconductor device according to claim 18,

wherein the semiconductor layer is sandwiched between a first oxide layer and a second oxide layer between the semiconductor layer and the first gate insulating layer, and

wherein the first oxide layer and the second oxide layer each include one or more metal elements included in the semiconductor layer.

24. The semiconductor device according to claim 18, wherein the gate electrode is located over the semiconductor layer.

25. The semiconductor device according to claim 18, wherein the nitrogen content is lower than or equal to 0.1 at. %.

26. A semiconductor device comprising:

a semiconductor layer;

a gate electrode overlapping with the semiconductor layer; and

a first insulating layer in contact with the semiconductor layer,

wherein the semiconductor layer includes an oxide semiconductor,

wherein the first insulating layer includes an oxide, and

wherein a spin density of the first insulating layer is at most 1.5×

10¹⁹ spins/cm³, the spin density is a spin density of a signal observed by electron spin resonance measurement, wherein a g value of the signal is 2.001 and a hyperfine coupling constant of the signal is approximately 5 mT.

27. The semiconductor device according to claim 26, wherein the oxide semiconductor is an In—

Ga—

Zn-based oxide.

28. The semiconductor device according to claim 26,

wherein the semiconductor layer includes crystals of the oxide semiconductor,

wherein each c-axis of the crystals is aligned in a direction perpendicular to a surface of the semiconductor layer, and

wherein each of the crystals is a non-single-crystal.

29. The semiconductor device according to claim 26,

wherein the gate electrode is located under the semiconductor layer, and

wherein the first insulating layer is located between the gate electrode and the semiconductor layer.

30. The semiconductor device according to claim 26, wherein the spin density of the first insulating layer is at most 1.1×

10¹⁸ spins/cm^3.

31. A semiconductor device comprising:

a semiconductor layer;

a gate electrode overlapping with the semiconductor layer; and

a first insulating layer in contact with the semiconductor layer,

wherein the semiconductor layer includes an oxide semiconductor,

wherein the first insulating layer includes an oxide, and

wherein a spin density of the first insulating layer is at most 1.5×

10¹⁹ spins/cm³, the spin density being derived from NO_2.

32. The semiconductor device according to claim 31, wherein the oxide semiconductor is an In—

Ga—

Zn-based oxide.

33. The semiconductor device according to claim 31,

wherein the semiconductor layer includes crystals of the oxide semiconductor,

wherein each c-axis of the crystals is aligned in a direction perpendicular to a surface of the semiconductor layer, and

wherein each of the crystals is a non-single-crystal.

34. The semiconductor device according to claim 31,

wherein the gate electrode is located under the semiconductor layer, and

wherein the first insulating layer is located between the gate electrode and the semiconductor layer.

35. The semiconductor device according to claim 31, wherein the spin density of the first insulating layer is at most 1.1×

10¹⁸ spins/cm^3.