Methods and systems for skew tolerance in and advanced detectors for vector signaling codes for chip-to-chip communication

• US 9,300,503 B1
• Filed: 03/15/2013
• Issued: 03/29/2016
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Holden, Brian, Shokrollahi, Amin, Singh, Anant
• Primary Examiner(s): Wong, Linda
• Application Number:
  US13/842,740
• Time in Patent Office: 1,110 Days
• Field of Search: 375/219, 375/220, 375/222, 375/295, 375/316, 375/324, 375/325, 375/340, 375/341
• US Class Current: 1/1
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: H04B 17/364 Delay profiles
• CPC Class Codes: H04B 3/00 Line transmission systems combined with near-field transmission systems H04B5/00
• CPC Class Codes: H04B 3/02 Details
• CPC Class Codes: H04B 5/26 using coils
• CPC Class Codes: H04B 5/72 for local intradevice communication
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0643 block codes
• CPC Class Codes: H04L 2001/0096 Channel splitting in point-to-point links
• CPC Class Codes: H04L 25/0268 with modulation and subsequent demodulation
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/03019 adaptive, i.e. capable of adjustment during data reception
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/4925 using balanced bipolar ternary codes
• CPC Class Codes: H04L 7/043 Pseudo-noise [PN] codes variable during transmission synchronisation of spread spectrum receivers H04B1/69
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Abstract

Advanced detectors for vector signaling codes are disclosed which utilize multi-input comparators, generalized on-level slicing, reference generation based on maximum swing, and reference generation based on recent values. Vector signaling codes communicate information as groups of symbols which, when transmitted over multiple communications channels, may be received as mixed sets of symbols from different transmission groups due to propagation time variations between channels. Systems and methods are disclosed which compensate receivers and transmitters for these effects and/or utilize codes having increased immunity to such variations, and circuits are described that efficiently implement their component functions.

Claims

1. A circuit for detection of codewords of a vector signaling code, the circuit comprising:

at least three transistor circuits configured to receive at least three inputs, respectively, each input associated with a symbol of a codeword of a ternary vector signaling code, each transistor circuit having an input weighting factor, and configured to generate a corresponding weighted input of a set of at least three weighted inputs;

two summing nodes, each summing node receiving one or more of the at least three weighted inputs as summing-node inputs, each summing node forming a respective summing-node value of a pair of summing-node values, each summing-node value representing a sum of the summing-node inputs; and

,

a differential comparator accepting the pair of summing-node values as comparator inputs, the differential comparator configured to produce a digital output indicating which summing-node value of the pair of summing-node values is larger.

2. The circuit of claim 1, wherein each input weighting factor is an integer number.

3. The circuit of claim 1, wherein each input weighting factor represents the a magnitude of a current path controlled by the input associated with said input weighting factor.

4. The circuit of claim 1, wherein each input weighting factor represents a capacitance of a circuit node charged in proportion to the input associated with said input weighting factor.

5. The apparatus of claim 1, wherein one of the at least three weighted inputs is an offset voltage.

6. The apparatus of claim 5, wherein the offset voltage is proportionate to the a maximum signal swing of one or more of the at least three inputs.

7. The apparatus of claim 5, wherein the offset voltage is proportionate to one or more previous input values.

8. The circuit of claim 5, further comprising:

a voltage divider configured to obtain intermediate reference levels to be used as the offset voltage; and

,

a storage circuit configured to store the intermediate reference levels.

9. The circuit of claim 8, wherein the storage circuit comprises a digital memory to store a digital representation of the intermediate reference levels, and a digital-analog converter to recreate the intermediate reference levels based on the digital representation of the intermediate reference levels.

10. The circuit of claim 9, further comprising a decoder configured to determine the offset voltage based on a previously transmitted symbol, the decoder comprising:

a storage element configured to store the previously transmitted symbols; and

,

a selection circuit configured to select an offset based on the stored previously transmitted symbols.

11. The circuit of claim 1, wherein each transistor circuit has a corresponding input weighting factor determined by one or more transistors receiving the respective input.

12. The circuit of claim 1, wherein each transistor circuit has a corresponding input weighting factor determined by a single transistor receiving the respective input, wherein a transistor characteristic of the single transistor is adjusted in accordance with the corresponding input weighting factor.

13. The circuit of claim 12, wherein the transistor characteristic is channel length.

14. The circuit of claim 12, wherein the transistor characteristic is transfer current.

15. An apparatus comprising:

a plurality of codeword detection circuits configured to decode symbols of codewords of at least a ternary vector signaling code by generating a set of digital output signals,

each codeword detection circuit comprising;

a set of n weighted inputs comprising a set of input weighting factors, wherein n is an integer greater than 2;

two summing nodes, each summing node configured to receive at least one of the n weighted inputs as summing-node inputs, each summing node configured to generate a respective summing-node value of a pair of summing-node values, each respective summing-node value representing a sum of the summing-node inputs; and

,

a differential comparator configured to produce a respective digital output of the set of digital outputs, the digital output indicating which summing-node value of the pair is larger; and

,

a detector configured to obtain the symbols of a codeword based on the set of digital output signals.

16. A circuit comprising:

at least three transistor circuits configured to receive at least three inputs, respectively, each input associated with a symbol of a codeword of a vector signaling code, each transistor circuit configured to generate a corresponding weighted input of a set of at least three weighted inputs, each weighted input having a respective input weighting factor of a set of at least three distinct input weighting factors;

two summing nodes, each summing node receiving one or more of the at least three weighted inputs as summing-node inputs, each summing node generating a respective summing-node value of a pair of summing-node values, each summing-node value representing a sum of the summing-node inputs; and

a differential comparator accepting the pair of summing-node values as comparator inputs, the differential comparator configured to produce a digital output indicating which summing-node value of the pair of summing-node values is larger.

17. The circuit of claim 16, wherein each input weighting factor is an integer number.

18. The circuit of claim 16, wherein each input weighting factor represents a magnitude of a current path controlled by the input associated with said input weighting factor.

19. The circuit of claim 16, wherein each input weighting factor represents a capacitance of a circuit node charged in proportion to the input associated with said input weighting factor.