Method and system for wafer level testing of semiconductor chips

• US 9,304,166 B2
• Filed: 07/16/2010
• Issued: 04/05/2016
• Est. Priority Date: 07/16/2010
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Zhaojun, Shao
• Primary Examiner(s): Phan, Huy Q
• Assistant Examiner(s): RHODES-VIVOUR, TEMILADE S
• Application Number:
  US12/837,596
• Publication Number:
  US 20120013359A1
• Time in Patent Office: 2,090 Days
• Field of Search: 324/750.15, 324/750.3, 324/762.01, 324/762.03, 324/762.05, 324/762.06, 702 57- 59, 714733-734
• US Class Current: 1/1
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/318563 Multiple simultaneous testing of subparts
• CPC Class Codes: H01L 21/00 Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00

Abstract

A system and method for wafer level testing of semiconductor chips are provided. In one embodiment, the system comprises a plurality of semiconductor chips disposed in a wafer, each semiconductor chip having at least one port for receiving test data and at least one connection disposed in a kerf region of the wafer between at least one port of a first semiconductor chip and at least one port of at least one second semiconductor chip in the plurality of semiconductor chips, wherein the first semiconductor chip is configured to send the test data to the at least one second semiconductor chip via the at least one connection. Additionally, the plurality of semiconductor chips may comprise at least one core logic configured to pass the test data to the at least one second semiconductor chip via the at least one connection.

Claims

1. A system for testing semiconductor chips comprising:

a plurality of semiconductor chips disposed in a wafer, each of the plurality of semiconductor chips having a first set of ports, a second set of ports, at least one test output port, at least one internal core logic, wherein at least one port of the first set of ports is for receiving test data;

at least one connection disposed in a kerf region of the wafer between at least one port of the second set of ports of a first semiconductor chip and at least one port of the first set of ports of at least one second semiconductor chip in the plurality of semiconductor chips;

wherein test data sent from a tester exclusively to the at least one port of the first set of ports of the first semiconductor chip is passed through an internal path of the first semiconductor chip and to the at least one port of the first set of ports of the at least one second semiconductor chip via the at least one connection,

wherein the internal core logic enables the internal path of the first semiconductor chip to connect the at least one port of the first set of ports for receiving test data to the at least one port of the second set of ports of the first semiconductor chip;

wherein the at least one test output port of each of the plurality of semiconductor chips is individually connected to the tester,

wherein the tester is external to the wafer.

2. The system of claim 1, wherein the plurality of semiconductor chips are identical to one another.

3. The system of claim 1, wherein the at least one connection comprises:

a first connection disposed in the kerf region between one of the second set of ports of the first semiconductor chip and one of the first set of ports of the at least one second semiconductor chip; and

a second connection disposed in the kerf region between a second one of the second set of ports of the first semiconductor chip and a second one of the first set of ports of the at least one second semiconductor chip.

4. The system of claim 3, wherein the first semiconductor chip is configured to send the test data to the at least one second semiconductor chip via the first connection and the second connection simultaneously.

5. The system of claim 1, wherein at least one port of the first set of ports of each of the plurality of semiconductor chips comprises at least one test input port.

6. The system of claim 5,

wherein the tester is an automated test equipment comprising:

at least one channel coupled to the at least one test input port of the first semiconductor chip; and

at least one channel coupled to the at least one test output port of the plurality of semiconductor chips.

7. The system of claim 6, wherein the first semiconductor chip is configured to receive the test data from the at least one channel of the automated test equipment at the at least one test input port of the first semiconductor chip.

8. The system of claim 7, wherein the first semiconductor is configured to send the test data received at the at least one test input port to the at least one test input port of the at least one second semiconductor chip via the at least one connection.

9. A method for testing semiconductor chips comprising:

providing a plurality of semiconductor chips in a wafer, each of the plurality of semiconductor chips comprising one or more first ports, one or more second ports, at least one output port, and an internal core logic;

connecting the one or more second ports of one or more of the plurality of semiconductor chips to at least one connection in a kerf region of the wafer;

sending test data from a tester exclusively to the one or more first ports of a first semiconductor chip in the plurality of semiconductor chips; and

receiving the test data from at least one channel of the tester to the one or more first ports of the first semiconductor chip;

passing the test data from the one or more first ports through an internal path of the first semiconductor chip to the one or more first ports of at least one second semiconductor chip via the at least one connection, the passing comprising connecting, by the internal core logic of the first semiconductor chip, the one or more first ports of the first semiconductor chip to the one or more second ports of the first semiconductor chip,

wherein the tester is external to the plurality of semiconductor chips.

10. The method of claim 9, wherein connecting the one or more second ports of the plurality of semiconductor chips to at least one connection in a kerf region of the wafer comprises:

connecting one or more of the second ports of the first semiconductor chip to one or more of the one or more first ports of the at least one second semiconductor chip via a first connection in the kerf region; and

connecting another one or more of the second ports of the first semiconductor chip to one or more of the one or more first ports of the at least one second semiconductor chip via a second connection in the kerf region.

11. The method of claim 10, wherein the one or more first ports are at least one test input port for receiving the test data.

12. The method of claim 10, wherein

the test data is sent to the one or more first ports of the at least one second semiconductor chip via the first connection and second connection simultaneously.

13. A system for testing semiconductor chips comprising:

a plurality of identical semiconductor chips disposed in a wafer, each of the plurality of semiconductor chips comprising a first set of ports, at least one port of the first set of ports for receiving test data, a second set of ports, at least one output port and at least one internal core logic;

at least one connection disposed in a kerf region of the wafer between at least one port of the second set of ports of a first semiconductor chip and at least one port of the first set of ports of at least one second semiconductor chip in the plurality of semiconductor chips,

wherein test data is sent from a tester exclusively to the at least one port of the first set of ports for receiving data of the first semiconductor chip passes internally through the first semiconductor to the at least one port of the second set of ports of the at least one second semiconductor chip via the at least one connection,

wherein the internal core logic of the first semiconductor chip selectively enables an internal path of the first semiconductor chip to connect the at least one port of the first set of ports for receiving test data of the first semiconductor chip to the at least one port of the second set of ports of the first semiconductor chip,

wherein the at least one output port of each of the plurality of semiconductor chips is individually connected to the tester, and

wherein the tester is external to the wafer.

14. The system of claim 13, wherein one or more of the second set of ports of the first semiconductor chip is coupled to one or more of the first set of ports of a second semiconductor chip via a first connection of the at least one connection and one or more of the second set of ports of the first semiconductor chip is coupled to one or more of the first set of ports of a third semiconductor chip via second connection of the at least one connection.

15. The system of claim 13, wherein the first semiconductor chip comprises:

a third set of ports coupled to the first set of ports of a third semiconductor chip in the at least one second semiconductor chip via a second connection disposed in a kerf region.

16. The system of claim 15, wherein the internal core logic selectively enables an internal path of the first semiconductor chip to connect at least one of the first set of ports for receiving test data to at least one of the third set of ports so as to pass the test data to the first set of ports of the third semiconductor chip via the second connection.

17. A method for testing semiconductor chips comprising:

providing a plurality of semiconductor chips in a wafer, each of the plurality of semiconductor chips comprising first set of ports, a second set of ports, and an internal core logic;

connecting at least one port of the second set of ports of a first semiconductor chip of the plurality of semiconductor chips to at least one connection in a kerf region of the wafer;

configuring the internal core logic to connect at least one of the first set of ports of the first semiconductor chip to at least one of the second set of ports of the first semiconductor chip connected to the at least one connection upon the first semiconductor chip entering a test mode;

sending test data from a tester exclusively to the at least one of the first set of ports of the first semiconductor chip in the plurality of semiconductor chips; and

passing the test data from the at least one port of the first set of ports of the first semiconductor chip internally through the first semiconductor chip to at the least one of the second ports of the first semiconductor chip and to at least one second semiconductor chip via the at least one connection,

wherein the tester is external to the plurality of semiconductor chips.

18. The method of claim 17, wherein sending test data from a tester to the at least one port of the first set of ports of the first semiconductor chip in the plurality of semiconductor chips comprises:

receiving the test data from at least one channel of the tester at the at least one of the first set of ports of the first semiconductor chip; and

sending the test data from the at least one of the first set of ports to the at least one of the second set of ports of the first semiconductor chip via at least one internal path.

19. The method of claim 17, wherein connecting at least one port of the second set of ports of the first semiconductor chip to the at least one connection in a kerf region of the wafer comprises:

connecting the at least one of second set of ports of the first semiconductor chip to at least one of the first ports of a second semiconductor chip of the at least one second semiconductor chip via a first subset of the at least one connection; and

connecting at least another one of the second set of ports of the first semiconductor chip to at least one of the first ports of a third semiconductor chip of the at least one second semiconductor chip via a second subset of the at least one connection.

20. The method of claim 19, wherein passing the test data from the at least one port of the first set of ports of the first semiconductor chip to the at least one port of the second set of ports of the first semiconductor chip and to at least one second semiconductor chip via the at least one connection comprises:

sending the test data from the at least one of the second set of ports of the first semiconductor chip to at least one of the first ports of the second semiconductor chip of the at least one second semiconductor chip via the first subset of the at least one connection; and

sending the test data from the at least another one of the second set of ports of the first semiconductor chip to at least one of the first ports of the third semiconductor chip of the at least one second semiconductor chip via the second subset of the at least one connection simultaneously.

21. The method of claim 17, the method further comprising:

configuring the internal core logic to connect at least one of the first set of ports of the first semiconductor chip to at least one of a third set of ports of the first semiconductor chip upon the first semiconductor chip entering a test mode.

22. The method of claim 21, further comprising:

connecting at least one of the third set of ports of the first semiconductor chip to at least one of the first ports of a third semiconductor chip of the at least one second semiconductor chip via a second subset of the at least one connection.

23. The method of claim 22, further comprising:

passing the test data from the at least one port of the first set of ports of the first semiconductor chip internally through the first semiconductor chip to at the least one of the third ports of the first semiconductor chip and to the third semiconductor chip of at least one second semiconductor chip via the second subset of the at least one connection;

sending the test data from at least one of the second set of ports of the first semiconductor chip to the at least one of the first set of ports of the second semiconductor chip of the at least one second semiconductor chip via the first subset of the at least one connection; and

sending the test data from the at least one of the third set of ports of the first semiconductor chip to at least one of the first set of ports of the third semiconductor chip of the at least one second semiconductor chip via the second subset of the at least one connection simultaneously.