Semiconductor device and operating method thereof
First Claim
Patent Images
1. A semiconductor device comprising:
- a controller configured to receive a request for a first memory device, determine whether or not a multi-bit error has occurred at a requested address of the first memory device, and process the request on a second memory device instead of the first memory device, when the multi-bit error has occurred,wherein the second memory device is configured to store an error address where the multi-bit error occurred at the first memory device prior to receiving the request and a normal data corresponding to the error address,wherein the controller processes the request for the first memory device when a single-bit error has occurred at the requested address of the first memory device, and registers multi-bit error occurrence information corresponding to the request address when a multi-bit error exists in data outputted from the first memory device, andwherein the second memory device is configured to store single-bit error occurrence information, and the controller removes soft error information in the single-bit error occurrence information stored in the second memory device.
1 Assignment
0 Petitions
Accused Products
Abstract
A semiconductor device includes a controller configured to receive a request for a first memory device, determine whether or not a multi-bit error has occurred at a requested address of the first memory device, and process the request on a second memory device instead of the first memory device, when the multi-bit error has occurred.
-
Citations
24 Claims
-
1. A semiconductor device comprising:
-
a controller configured to receive a request for a first memory device, determine whether or not a multi-bit error has occurred at a requested address of the first memory device, and process the request on a second memory device instead of the first memory device, when the multi-bit error has occurred, wherein the second memory device is configured to store an error address where the multi-bit error occurred at the first memory device prior to receiving the request and a normal data corresponding to the error address, wherein the controller processes the request for the first memory device when a single-bit error has occurred at the requested address of the first memory device, and registers multi-bit error occurrence information corresponding to the request address when a multi-bit error exists in data outputted from the first memory device, and wherein the second memory device is configured to store single-bit error occurrence information, and the controller removes soft error information in the single-bit error occurrence information stored in the second memory device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. A system comprising a control device configured to control a semiconductor memory device,
wherein the control device comprises: -
a register configured to store an error address at which a multi-bit error has occurred in the semiconductor memory device and a normal data corresponding to the error address; and a controller configured to receive a request for the semiconductor memory device, determine whether or not a multi-bit error has occurred at a requested address of the semiconductor memory device, and process the request on the register instead of the semiconductor memory device when a multi-bit error has occurred, wherein the register is configured to store the error address and the normal data prior to receiving the request, the register further stores single-bit error occurrence information indicating an address at which a single-bit error has occurred in the semiconductor memory device and data corresponding to the address, wherein the controller controls the register to check whether or not a single-bit error has occurred at the requested address during the request for the semiconductor memory device, processes the request for the semiconductor memory device when a single-bit error has occurred at the requested address, and stores multi-bit error occurrence information corresponding to the requested address in the register when a multi-bit error occurred in data outputted from the semiconductor memory device as a result obtained by processing the request for the semiconductor memory device, and wherein the controller removes soft error information in the single-bit error occurrence information stored in the register. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
-
Specification