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Method for flip chip packaging co-design

  • US 9,305,131 B2
  • Filed: 11/07/2014
  • Issued: 04/05/2016
  • Est. Priority Date: 12/03/2013
  • Status: Active Grant
First Claim
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1. A method for flip chip packaging co-design, the method comprising steps of:

  • providing an Input/Output (I/O) pad information of a chip and a connection information of a PCB;

    performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB;

    utilizing a redistribution layer (RDL) routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result;

    performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and

    performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.

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