Method for flip chip packaging co-design

• US 9,305,131 B2
• Filed: 11/07/2014
• Issued: 04/05/2016
• Est. Priority Date: 12/03/2013
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Fang, Jia-Wei, Huang, Shen-Yu
• Primary Examiner(s): Ngo, Brian
• Application Number:
  US14/535,328
• Publication Number:
  US 20150154336A1
• Time in Patent Office: 515 Days
• Field of Search: 716/111, 716/118, 716/120, 716/126
• US Class Current: 1/1
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 2115/12 Printed circuit boards [PCB] or multi-chip modules [MCM]
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H01L 2224/0612 Layout
• CPC Class Codes: H01L 2224/1412 Layout
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.

Claims

1. A method for flip chip packaging co-design, the method comprising steps of:

providing an Input/Output (I/O) pad information of a chip and a connection information of a PCB;

performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB;

utilizing a redistribution layer (RDL) routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result;

performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and

performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.

2. The method of claim 1, further comprising:

providing a RDL routing information of the chip.

3. The method of claim 2, wherein the step of performing the first I/O pad placement is performed further according to the RDL routing information of the chip.

4. The method of claim 1, further comprising:

providing a power domain information of the chip.

5. The method of claim 4, wherein the step of performing the first I/O pad placement is performed further according to the power domain information of the chip.

6. The method of claim 4, further comprising:

utilizing an IR drop analysis device to perform a bump pad count/location analysis for a plurality of power domains of the chip to generate a bump pad count/location analysis result.

7. The method of claim 6, wherein the step of performing the bump pad planning for the package is performed further according to the bump pad count/location analysis result of the chip.

8. The method of claim 1, further comprising:

reviewing the PCB constraints of the flip chip after performing the bump pad planning for the package;

remaining the generated bump pad planning result if the generated bump pad planning result meets the PCB constraints; and

performing the bump pad planning for the package again if the generated bump pad planning result fails to meet the PCB constraints.

9. The method of claim 1, further comprising:

reviewing the chip constraints of the flip chip after performing the second I/O pad placement for the chip;

remaining the I/O pad placement result if the generated I/O pad placement result meets the chip constraints; and

performing the I/O pad placement for the chip again if the generated I/O pad placement result fails to meet the chip constraints.

10. The method of claim 1, further comprising:

determining whether the I/O pad placement result converges to a final I/O pad placement for the flip chip by performing an IR drop analysis for the I/O pad placement result.

11. The method of claim 10, further comprising:

performing the bump pad planning for the package again if the I/O pad placement result fails to pass the IR drop analysis; and

determining the I/O pad placement result converges to the final I/O pad placement for the flip chip if the I/O pad placement result passes the IR drop analysis.

12. The method of claim 10, further comprising:

utilizing the RDL routing analysis device to perform the bump pad pitch analysis for the first I/O pad placement of the chip again if the I/O pad placement result fails to pass the IR drop analysis; and

determining the I/O pad placement result converges to the final I/O pad placement for the flip chip if the I/O PAD placement result passes the IR drop analysis.

13. A method for flip chip packaging co-design, the method comprising steps of:

providing a power domain information of the chip, an I/O pad information of a chip, and a connection information of a PCB;

performing a first I/O PAD placement according to the power domain information of the chip, the I/O pad information of the chip, and the connection information of the PCB;

utilizing an IR drop analysis device to perform a bump pad count/location analysis for a plurality of power domains of the chip to generate a bump pad count/location analysis result;

performing a bump pad planning for a package according to the bump pad count/location analysis result to generate a bump pad planning result; and

performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.

14. The method of claim 13, further comprising:

providing a redistribution layer (RDL) routing information of the chip.

15. The method of claim 14, wherein the step of performing the first I/O pad placement is performed further according to the RDL routing information of the chip.

16. The method of claim 13, wherein the step of performing the bump pad planning for the package is performed further according to the bump pad count/location analysis result of the chip.

17. The method of claim 13, further comprising:

reviewing the PCB constraints of the flip chip after performing the bump pad planning for the package;

remaining the generated bump pad planning result if the generated bump pad planning result meets the PCB constraints; and

performing the bump pad planning for the package again if the generated bump pad planning result fails to meet the PCB constraints.

18. The method of claim 13, further comprising:

reviewing the chip constraints of the flip chip after performing the second I/O pad placement for the chip;

remaining the I/O pad placement result if the generated I/O pad placement result meets the chip constraints; and

performing the I/O pad placement for the chip again if the generated I/O pad placement result fails to meet the chip constraints.

19. The method of claim 13, further comprising:

determining whether the I/O pad placement result converges to a final I/O pad placement for the flip chip by performing an IR drop analysis for the I/O pad placement result.

20. The method of claim 19, further comprising:

performing the bump pad planning for the package again if the I/O pad placement result fails to pass the IR drop analysis; and

determining the I/O pad placement result converges to the final I/O pad placement for the flip chip if the I/O pad placement result passes the IR drop analysis.

21. The method of claim 19, further comprising:

utilizing the RDL routing analysis device to perform the bump pad pitch analysis for the first I/O pad placement of the chip again if the I/O pad placement result fails to pass the IR drop analysis; and

determining the I/O pad placement result converges to the final I/O pad placement for the flip chip if the I/O pad placement result passes the IR drop analysis.