System and method for selective application and reconciliation of hierarchical ordered sets of circuit design constraints within a circuit design editor

• US 9,305,133 B1
• Filed: 09/04/2014
• Issued: 04/05/2016
• Est. Priority Date: 09/04/2014
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Ghosh, Sandipan, Khanna, Anjna
• Primary Examiner(s): Lee, Eric
• Application Number:
  US14/476,807
• Time in Patent Office: 579 Days
• Field of Search: 716/139
• US Class Current: 1/1
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A system and method are provided for selective application and expeditious reconciliation of constraints within a hierarchy of circuit design constraints. A semi-transparent constraint editor user interface is provided in contextual registration near detected violations during editing interactions with a circuit design. The constraint editor provides a simplified representation of a lookup order of a hierarchy of constraints applicable to an object related to the detected violation. The user is then able to easily modify constrained values within the lookup order, modify the lookup order, or modify the editing interaction to reconcile the violation expeditiously all while maintaining context within the circuit design.

Claims

1. A method for selective application and reconciliation of hierarchical ordered sets of circuit design constraints within a circuit design editor, the sets respectively relating to different hierarchical portions of the circuit design, the method comprising:

(A) executing a computer processor-based circuit design editor to graphically render on a display device at least a portion of a circuit design within a circuit editor user-interface, the circuit design including a plurality of interconnected circuit objects maintained in a computer memory operably coupled to the computer processor;

(B) detecting any violation of at least one circuit design constraint of the hierarchical sets of constraints responsive to an editing interaction executed on the circuit design editor with a circuit object of the displayed portion of the circuit design within the circuit editor user-interface;

(C) graphically indicating a violating object relating to a detected violation of at least one circuit design constraint;

(D) temporarily arresting execution of circuit editing operations by the circuit design editor and graphically rendering on the display device a constraint interface concurrently with the graphic rendering of the circuit design portion in the circuit editor user-interface, the constraint interface defining a graphic window adaptively superimposed in contextually registered and variably positioned manner proximate the violating object in the circuit design portion as graphically rendered, the constraint interface identifying to a user;

a type of the detected violation and a hierarchical source of the circuit design constraint violated; and

,

(E) responsive to a user input within the circuit editor user-interface, selectively;

(1) modifying the editing interaction, (2) modifying the application of at least one circuit design constraint of the hierarchical set of constraints, or (3) modifying at least one circuit design constraint of the hierarchical set of constraints, to reconcile the detected violation.

2. The method as recited in claim 1, wherein graphically rendering the constraint interface includes rendering the constraint interface in semi-transparent manner superimposed over the displayed portion of the circuit design within the circuit editor user-interface to thereby generate a composite display including the constraint interface and the displayed portion of the circuit design at least partially visible through the constraint interface.

3. The method as recited in claim 2, wherein the detecting any violation of at least one circuit design constraint of the hierarchical sets of constraints includes identifying all constraints and respectively constrained values relating to the violating object to establish a constraint lookup-order.

4. The method as recited in claim 3, wherein the graphically rendering the constraint interface includes graphically rendering the constraint lookup-order of the hierarchical sets of circuit design constraints respectively relating to identified hierarchical portions of the circuit design including at least a portion of:

an object, a device, a net portion, a grouping of devices, a circuit design layer, the circuit design, and a fabrication technology for the circuit design.

5. The method as recited in claim 4, wherein the graphically rendering the constraint interface includes establishing an interactive constrained-value-setting portion for entry of a value by a user to modify a value of at least one selected constraint values of at least one circuit design constraint in the constraint lookup order.

6. The method as recited in claim 5, wherein the graphically rendering the constraint interface includes graphically rendering a textual explanation and graphical illustration of the type of circuit design constraint relating to the detected violation.

7. The method as recited in claim 6, wherein the identifying to a user a hierarchical source of the circuit design constraint violated includes:

graphically indicating a circuit design constraint violated in the constraint lookup order according to a parameter of the violating object relative to a constrained value of the violated circuit design constraint.

8. The method as recited in claim 7, wherein the identifying the violating object relating to a detected violation includes:

detecting a plurality of violations;

detecting a relationship between each of the detected violations and a respective violating object; and

,

graphically rendering a visual indicia proximate the violating object within the displayed portion of the circuit design, the visual indicia being user selectable to identify a violating object.

9. The method as recited in claim 8, wherein the graphically rendering the constraint interface in contextual registration proximate the violating object is performed according to a user selection of the user-selectable visual indicia.

10. The method as recited in claim 9, wherein the user-selectable visual indicia is graphically rendered to overlay the displayed portion of the circuit design within the circuit editor user interface and is selected from one of an annotation and a marker.

11. The method as recited in claim 10, wherein a debugging mode is established within the circuit editor user interface responsive to a user interaction, the debugging mode inhibiting user interactions with circuit objects and remapping user interactions to the user-selectable visual indicia.

12. The method as recited in claim 1, wherein the detecting any violation includes:

detecting all violations; and

,

selecting a subset of the plurality of violations according to a predetermined set of relevance factors.

13. The method as recited in claim 12, wherein the identifying a violating object relating to a detected violation includes:

graphically identifying by annotating with a visual indicia at least one violating object in the displayed portion of the circuit design responsive to the selected subset of detected violations; and

,

accepting a user selection of one of the visual indicia to identify the violating object.

14. A circuit editor system having selective application and reconciliation of hierarchical ordered sets of circuit design constraints, the sets respectively relating to different hierarchical portions of a circuit design, the system comprising:

a design database stored in a memory maintaining the circuit design including a plurality of interconnected circuit objects and the hierarchical ordered sets of circuit design constraints;

a computer processor-based circuit editor module operably coupled to the design database, the circuit editor module retrieving at least a portion of the plurality of interconnected circuit objects and graphically rendering circuit objects of at least a corresponding portion of the circuit design within a circuit editor user-interface on a display and receiving user editing interactions with at least one circuit object of the circuit design;

a computer processor-based violation detection module operably coupled to the circuit editor module and the design database, the violation detection module executing to detect any violation of at least one circuit design constraint of the hierarchical sets of constraints responsive to an editing interaction with a circuit object of the displayed portion of the circuit design within the circuit editor user-interface by a user and graphically indicate a violating circuit object relating to a detected violation of at least one circuit design constraint; and

,

a computer processor-based constraint module operably coupled to the violation detection module and the design database executing to;

retrieve circuit design constraints and circuit object data relating to the violating circuit object from the design database,

temporarily arresting execution of circuit editing operations by the circuit editor module and graphically render on the display a constraint interface concurrently with the graphic rendering of the circuit design portion in the circuit editor user-interface, the constraint interface defining a graphic window adaptively superimposed in contextually registered and variably positioned manner proximate the violating object in the circuit design portion as graphically rendered, the constraint interface identifying to a user;

a type of the detected violation and an hierarchical source of the circuit design constraint violated, and

responsive to a user input within the circuit editor user-interface, selectively;

(1) modify the editing interaction, (2) modify the application of at least one circuit design constraint of the hierarchical set of constraints, or (3) modify at least one circuit design constraint of the hierarchical set of constraints, to reconcile the detected violation.

15. The system as recited in claim 14, wherein the constraint module selectively modifies circuit object data or circuit design constraints of the hierarchical set of constraints responsive to user input within the circuit editor user-interface.

16. The system as recited in claim 15, wherein the constraint module graphically renders the constraint interface in semi-transparent manner with partial-opacity superimposed over the displayed portion of the circuit design within the circuit editor user-interface to thereby generate a composite display including the constraint interface and the displayed portion of the circuit design at least partially visible through the constraint interface.

17. A computer processor-based circuit editor system having selective application and reconciliation of hierarchical ordered sets of circuit design constraints, the sets respectively relating to different hierarchical portions of a circuit design, the system comprising:

a design database stored in a computer memory maintaining a data representation of the circuit design including a plurality of interconnected circuit objects and the hierarchical ordered sets of circuit design constraints relating to the plurality of interconnected circuit objects;

a circuit editor executing in the computer processor, the circuit editor retrieving at least a portion of the plurality of interconnected circuit objects from the design database in the computer memory and graphically rendering corresponding circuit objects of at least a portion of the circuit design within a circuit editor user-interface on the display device and receiving user editing interactions with the portion of the circuit design from the user interface device;

a violation detector executing in the computer processor to detect any violation of at least one circuit design constraint of the hierarchical sets of constraints responsive to a user editing interaction with a circuit object of the displayed portion of the circuit design within the circuit editor user-interface by a user manipulating the user interface device, and graphically indicating a violating circuit object relating to a detected violation; and

,

a constraint editor executing in the computer processor to temporarily arrest execution of circuit editing operations by the circuit editor and graphically render on the display device a constraint interface concurrently with the graphic rendering of the circuit design portion in the circuit editor user-interface, the constraint interface defining a graphic window adaptively superimposed in contextually registered and variably positioned manner proximate violating object in the circuit design portion as graphically rendered, the constraint interface identifying to a user;

a type of the detected violation and an hierarchical source of the circuit design constraint violated, and responsive to a user input within the circuit editor user-interface, selectively;

(1) modifying the violating object in the design database, (2) modifying the application of at least one circuit design constraint of the hierarchical set of constraints, or (3) modifying at least one circuit design constraint of the hierarchical set of constraints, to reconcile the detected violation.

18. The system as recited in claim 17, wherein the constraint editor graphically rendering the constraint interface includes rendering the constraint interface in semi-transparent manner with partial-opacity superimposed over the displayed portion of the circuit design within the circuit editor user-interface to thereby generate a composite display including the constraint interface and the displayed portion of the circuit design at least partially visible through the constraint interface.

19. The system as recited in claim 18, wherein the violation detector executes to detect any violation of at least one circuit design constraint of the hierarchical sets of constraints includes identifying all constraints and respectively constrained values relating to the violating object to establish a constraint lookup-order.

20. The system as recited in claim 19, wherein the constraint editor executing to graphically render the constraint interface graphically renders the constraint lookup-order of the hierarchical sets of circuit design constraints respectively relating to identified hierarchical portions of the circuit design including a plurality of:

an object, a device, a net portion, a grouping of devices, a circuit design layer, the circuit design, and a fabrication technology for the circuit design.