Discrete three-dimensional vertical memory comprising off-die address/data-translator

• US 9,305,604 B2
• Filed: 05/08/2015
• Issued: 04/05/2016
• Est. Priority Date: 09/01/2011
• Status: Active Grant

• Current Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Original Assignee: Guobiao Zhang, Hangzhou Haicun Information Technology Co., Ltd.
• Inventors: Zhang, Guobiao
• Primary Examiner(s): Lee, Kyoung
• Assistant Examiner(s): Mehta, Ratisha
• Application Number:
  US14/707,023
• Publication Number:
  US 20150269970A1
• Time in Patent Office: 333 Days
• Field of Search: 257/296, 257/303, 257/311, 257/314, 257/315, 257/686, 438/238, 438/241, 438/257, 438/258, 438/262, 438/264, 438/266
• US Class Current: 1/1
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0023 Address circuits or decoders
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/14 Word line organisation; Word line lay-out
• CPC Class Codes: H01L 2224/13101 the principal constituent melting at a temperature of less than 400°C
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1064 : Electrical connections provided on a side surface of one or more of the containers
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

The present invention discloses a discrete three-dimensional vertical memory (3D-M_V). It comprises at least a 3D-array die and at least an A/D-translator die. The 3D-array die comprises a plurality of vertical memory strings. At least an address/data (A/D)-translator for the 3D-array die is located on the A/D-translator die instead of the 3D-array die. The 3D-array die and the A/D-translator die have substantially different back-end-of-line (BEOL) structures.

Claims

1. A discrete three-dimensional vertical memory (3D-M_V), comprising:

a 3D-array die comprising at least a 3D-M_V array, wherein said 3D-M_V array comprises a plurality of vertical memory strings, each of said vertical memory strings comprising a plurality of vertically stacked memory cells;

an A/D-translator die comprising at least a portion of an address/data-translator, wherein said portion of said address/data-translator is absent from said 3D-array die;

means for coupling said 3D-array die and said A/D-translator die;

wherein the number of memory cells on each of said vertical memory strings in said 3D-array die is substantially more than the number of interconnect levels in said A/D-translator die; and

, said 3D-array die and said A/D-translator die are separate dice.

2. The memory according to claim 1, wherein said 3D-array die further comprises at least a peripheral circuit located outside said 3D-M_V array, and the number of interconnect levels of said A/D-translator die is more than the number of interconnect levels of said peripheral circuit.

3. The memory according to claim 1, wherein said 3D-array die further comprises at least a peripheral circuit located outside said 3D-M_V array, and said peripheral circuit and said A/D-translator die comprise different interconnect materials.

4. The memory according to claim 1, wherein said 3D-M_V is a vertical-NAND.

5. The memory according to claim 1, wherein each of said memory cells comprises at least a vertical transistor.

6. The memory according to claim 1, wherein said 3D-M_V is a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).

7. The memory according to claim 1, wherein said 3D-array die and said A/D-translator die are located in a memory package, a memory module, a memory card, or a solid-state drive.

8. The memory according to claim 1, further comprising another 3D-array die including at least another 3D-M_V array, wherein said A/D-translator die comprises at least another portion of another address/data-translator for said another 3D-array die.

9. The memory according to claim 1, wherein said address/data-translator comprises at least an address translator and/or a data translator.

10. A discrete three-dimensional vertical memory (3D-M_V), comprising:

a 3D-array die comprising at least a 3D-M_V array and a peripheral circuit located outside said 3D-M_V array, wherein said 3D-M_V array comprises a plurality of vertical memory strings, each of said vertical memory strings comprising a plurality of vertically stacked memory cells;

an A/D-translator die comprising at least a portion of an address/data-translator, wherein said portion of said address/data-translator is absent from said 3D-array die;

means for coupling said 3D-array die and said A/D-translator die;

wherein said peripheral circuit and said A/D-translator die comprise different interconnect materials; and

, said 3D-array die and said A/D-translator die are separate dice.

11. The memory according to claim 10, wherein said peripheral circuit comprises high-temperature interconnect materials.

12. The memory according to claim 10, wherein said A/D-translator die comprises high-speed interconnect materials.

13. The memory according to claim 10, wherein the number of memory cells on each of said vertical memory strings in said 3D-array die is substantially more than the number of interconnect levels in said A/D-translator die.

14. The memory according to claim 10, wherein the number of interconnect levels of said A/D-translator die is more than the number of interconnect levels of said peripheral circuit.

15. The memory according to claim 10, wherein said 3D-M_V is a vertical-NAND.

16. The memory according to claim 10, wherein each of said memory cells comprises at least a vertical transistor.

17. The memory according to claim 10, wherein said 3D-M_V is a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM).

18. The memory according to claim 10, wherein said 3D-array die and said A/D-translator die are located in a memory package, a memory module, a memory card, or a solid-state drive.

19. The memory according to claim 10, further comprising another 3D-array die including at least another 3D-M_V array, wherein said A/D-translator die comprises at least another portion of another address/data-translator for said another 3D-array die.

20. The memory according to claim 10, wherein said address/data-translator comprises at least an address translator and/or a data translator.