Discrete three-dimensional vertical memory comprising off-die address/data-translator
First Claim
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1. A discrete three-dimensional vertical memory (3D-MV), comprising:
- a 3D-array die comprising at least a 3D-MV array, wherein said 3D-MV array comprises a plurality of vertical memory strings, each of said vertical memory strings comprising a plurality of vertically stacked memory cells;
an A/D-translator die comprising at least a portion of an address/data-translator, wherein said portion of said address/data-translator is absent from said 3D-array die;
means for coupling said 3D-array die and said A/D-translator die;
wherein the number of memory cells on each of said vertical memory strings in said 3D-array die is substantially more than the number of interconnect levels in said A/D-translator die; and
, said 3D-array die and said A/D-translator die are separate dice.
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Abstract
The present invention discloses a discrete three-dimensional vertical memory (3D-MV). It comprises at least a 3D-array die and at least an A/D-translator die. The 3D-array die comprises a plurality of vertical memory strings. At least an address/data (A/D)-translator for the 3D-array die is located on the A/D-translator die instead of the 3D-array die. The 3D-array die and the A/D-translator die have substantially different back-end-of-line (BEOL) structures.
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Citations
20 Claims
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1. A discrete three-dimensional vertical memory (3D-MV), comprising:
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a 3D-array die comprising at least a 3D-MV array, wherein said 3D-MV array comprises a plurality of vertical memory strings, each of said vertical memory strings comprising a plurality of vertically stacked memory cells; an A/D-translator die comprising at least a portion of an address/data-translator, wherein said portion of said address/data-translator is absent from said 3D-array die; means for coupling said 3D-array die and said A/D-translator die; wherein the number of memory cells on each of said vertical memory strings in said 3D-array die is substantially more than the number of interconnect levels in said A/D-translator die; and
, said 3D-array die and said A/D-translator die are separate dice. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A discrete three-dimensional vertical memory (3D-MV), comprising:
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a 3D-array die comprising at least a 3D-MV array and a peripheral circuit located outside said 3D-MV array, wherein said 3D-MV array comprises a plurality of vertical memory strings, each of said vertical memory strings comprising a plurality of vertically stacked memory cells; an A/D-translator die comprising at least a portion of an address/data-translator, wherein said portion of said address/data-translator is absent from said 3D-array die; means for coupling said 3D-array die and said A/D-translator die; wherein said peripheral circuit and said A/D-translator die comprise different interconnect materials; and
, said 3D-array die and said A/D-translator die are separate dice. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification