Discrete three-dimensional vertical memory
First Claim
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1. A discrete three-dimensional vertical memory (3D-MV), comprising:
- a 3D-array die comprising at least a 3D-MV array, wherein said 3D-MV array comprises a plurality of vertical memory strings, each of said vertical memory strings comprising a plurality of vertically stacked memory cells;
a peripheral-circuit die comprising at least an off-die peripheral-circuit component of said 3D-MV array, wherein said off-die peripheral-circuit component is absent from said 3D-array die;
means for coupling said 3D-array die and said peripheral-circuit die;
wherein the number of memory cells on each of said vertical memory strings in said 3D-array die is at least twice as much as the number of interconnect levels in said peripheral-circuit die; and
, said 3D-array die and said peripheral-circuit die are separate dice.
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Abstract
The present invention discloses a discrete three-dimensional vertical memory (3D-MV). It comprises at least a 3D-array die and at least a peripheral-circuit die. The 3D-array die comprises a plurality of vertical memory strings. At least an off-die peripheral-circuit component of the 3D-MV arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures.
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6 Claims
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1. A discrete three-dimensional vertical memory (3D-MV), comprising:
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a 3D-array die comprising at least a 3D-MV array, wherein said 3D-MV array comprises a plurality of vertical memory strings, each of said vertical memory strings comprising a plurality of vertically stacked memory cells; a peripheral-circuit die comprising at least an off-die peripheral-circuit component of said 3D-MV array, wherein said off-die peripheral-circuit component is absent from said 3D-array die; means for coupling said 3D-array die and said peripheral-circuit die; wherein the number of memory cells on each of said vertical memory strings in said 3D-array die is at least twice as much as the number of interconnect levels in said peripheral-circuit die; and
, said 3D-array die and said peripheral-circuit die are separate dice. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification