Semiconductor device and method for driving the same

• US 9,305,630 B2
• Filed: 07/15/2014
• Issued: 04/05/2016
• Est. Priority Date: 07/17/2013
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kurokawa, Yoshiyuki
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US14/331,732
• Publication Number:
  US 20150023114A1
• Time in Patent Office: 630 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

One of a source and a drain of a first oxide semiconductor (OS) transistor is connected to a gate of a second OS transistor and one electrode of a first capacitor. One of a source and a drain of the second OS transistor is connected to one electrode of a second capacitor and one of a source and a drain of a Si transistor. The gate of the second OS transistor serves as a charge retention node. Charge injection and retention at this node is controlled by the first OS transistor. The other of the source and the drain of the second OS transistor is connected to a wiring applying a high potential, and a potential of the second capacitor that corresponds to the write data is maintained. A signal corresponding to the write data is read by the Si transistor.

Claims

1. A semiconductor device comprising a memory element comprising:

a first transistor;

a second transistor;

a third transistor;

a first capacitor;

a second capacitor;

a first line;

a second line;

a third line;

a fourth line; and

a fifth line,

wherein;

one of a source and a drain of the first transistor is electrically connected to the first line;

the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the first capacitor;

a gate of the first transistor is electrically connected to the second line;

one of a source and a drain of the second transistor is electrically connected to the third line;

the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and one electrode of the second capacitor;

the other of the source and the drain of the third transistor is electrically connected to the fourth line;

a gate of the third transistor is electrically connected to the fifth line; and

a channel formation region of the first transistor includes an oxide semiconductor,

wherein a thickness of a gate insulating layer of the second transistor is larger than a thickness of a gate insulating layer of the third transistor.

2. The semiconductor device according to claim 1, wherein:

the one electrode of the first capacitor and the one electrode of the second capacitor are located in a same plane; and

the other electrode of the first capacitor and the other electrode of the second capacitor are located in a same plane.

3. The semiconductor device according to claim 1, wherein:

a channel formation region of the second transistor includes silicon; and

the channel formation region of the second transistor and a channel formation region of the third transistor are located in different planes.

4. The semiconductor device according to claim 1, wherein a channel formation region of the second transistor includes an oxide semiconductor.

5. The semiconductor device according to claim 1, wherein the channel formation region of the first transistor and a channel formation region of the second transistor are located in a same plane.

6. The semiconductor device according to claim 1, wherein:

the other electrode of the first capacitor is electrically connected to a ground line; and

the other electrode of the second capacitor is electrically connected to the ground line.

7. The semiconductor device according to claim 1, wherein:

the first line is a data line;

the second line is a write selection line;

the third line is configured to be supplied with a constant potential;

the fourth line is a read data line; and

the fifth line is a read selection line.

8. The semiconductor device according to claim 1, wherein a channel formation region of the second transistor includes silicon.

9. The semiconductor device according to claim 1, wherein a channel formation region of the third transistor includes silicon.

10. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a first capacitor;

a second capacitor;

a first line;

a second line;

a third line;

a fourth line; and

a fifth line,

wherein;

one of a source and a drain of the first transistor is electrically connected to the first line;

the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor and one electrode of the first capacitor;

a gate of the first transistor is electrically connected to the second line;

one of a source and a drain of the second transistor is electrically connected to the third line;

the other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of the third transistor and one electrode of the second capacitor;

the other of the source and the drain of the third transistor is electrically connected to the fourth line;

a gate of the third transistor is electrically connected to the fifth line;

a channel formation region of the first transistor includes an oxide semiconductor;

the other electrode of the first capacitor is electrically connected to a ground line;

the other electrode of the second capacitor is electrically connected to the ground line;

the first line is a data line;

the second line is a write selection line;

the third line is configured to be supplied with a constant potential;

the fourth line is a read data line;

the fifth line is a read selection line;

a channel formation region of the third transistor includes single crystal silicon; and

a thickness of a gate insulating layer of the second transistor is larger than a thickness of a gate insulating layer of the third transistor.

11. The semiconductor device according to claim 10,

wherein:

the one electrode of the first capacitor and the one electrode of the second capacitor are located in a same plane; and

the other electrode of the first capacitor and the other electrode of the second capacitor are located in a same plane.

12. The semiconductor device according to claim 10,

wherein:

a channel formation region of the second transistor includes silicon; and

the channel formation region of the second transistor and the channel formation region of the third transistor are located in different planes.

13. The semiconductor device according to claim 10, wherein a channel formation region of the second transistor includes an oxide semiconductor.

14. The semiconductor device according to claim 10, wherein the channel formation region of the first transistor and a channel formation region of the second transistor are located in a same plane.

15. The semiconductor device according to claim 10, wherein a channel formation region of the second transistor includes silicon.

16. A method for driving a semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a first node;

a second node;

a first line; and

a read data line, wherein the first node is electrically connected to one of a source and a drain of the first transistor and a gate of the second transistor, the second node is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the third transistor, the first line is electrically connected to the other of the source and the drain of the second transistor, the read data line is electrically connected to the other of the source and the drain of the third transistor, and a potential is supplied to the first line, the method comprising the steps of;

turning on the first transistor so as to write data in the first node;

turning off the first transistor so as to store the data in the first node;

holding a reading potential in the second node, wherein a level of the reading potential is controlled by the data that controls a conduction state of the second transistor;

turning on the third transistor so as to electrically connect the second node and the read data line that is in an electrically floating state, thereby reading a first potential of the read data line, the first potential being changed by the reading potential; and

turning off the third transistor so as to restore the reading potential in the second node in accordance with the data in the first node.

17. The method for driving a semiconductor device, according to claim 16, wherein the reading potential is supplied to the second node via the second transistor and the third transistor.

18. The method for driving a semiconductor device, according to claim 16, wherein the read data line being in the electrically floating state has a second potential that is lower than the reading potential.