Electronic device using group III nitride semiconductor having specified dislocation density, oxygen/electron concentration, and active layer thickness

• US 9,305,772 B2
• Filed: 08/14/2014
• Issued: 04/05/2016
• Est. Priority Date: 04/07/2006
• Status: Active Grant

• Current Assignee: Seoul Semiconductor Co., Ltd.
• Original Assignee: Seoul Semiconductor Co., Ltd., SixPoint Materials, Inc.
• Inventors: Hashimoto, Tadao
• Primary Examiner(s): Bradford, Peter
• Application Number:
  US14/460,097
• Publication Number:
  US 20150014818A1
• Time in Patent Office: 600 Days
• Field of Search: 438/503, 257/615
• US Class Current: 1/1
• CPC Class Codes: C23C 16/303 Nitrides
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02584 Delta-doping
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02623 Liquid deposition
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/201 including two or more compounds , e.g. alloys H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7784 with delta or planar doped donor layer H01L29/7785 takes precedence
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8122 : Vertical transistors SIT, PBT H01L29/7722
• CPC Class Codes: H01L 29/8611 : Planar PN junction diodes
• CPC Class Codes: H01L 29/872 : Schottky diodes

Abstract

The present invention discloses an electronic device using a group III nitride substrate fabricated via the ammonothermal method. By utilizing the high-electron concentration of ammonothermally grown substrates having the dislocation density less than 10⁵ cm⁻², combined with a high-purity active layer of Ga_1-x-yAl_xIn_yN (0≦x≦1, 0≦y≦1) grown by a vapor phase method, the device can attain high level of breakdown voltage as well as low on-resistance. To realize a good matching between the ammonothermally grown substrate and the high-purity active layer, a transition layer is optionally introduced. The active layer is thicker than a depletion region created by a device structure in the active layer.

Claims

1. An electronic device comprising a substrate of Ga_1-x1-y1Al_x1In_y1N (0≦

x1≦

1, 0≦

y1≦

1), an active layer of Ga_1-x2-y2Al_x2In_y2N (0≦

x2≦

1, 0≦

y2≦

1) on a first side of the substrate, a back ohmic contact on a second side opposite to the first side of the substrate, and a depletion region having a depth in the active layer, wherein;

(a) the substrate has a dislocation density of less than 10⁵ cm<sup>−

2</sup>;

(b) the substrate has an electron concentration or an oxygen concentration greater than 10¹⁸ cm<sup>−

3</sup>;

(c) the active layer has an electron concentration or an oxygen concentration less than 10¹⁸ cm<sup>−

3</sup>; and

(d) the depletion region does not extend into the substrate for any applied voltage within an operation range of the device, and the depletion region has a Schottky contact or a metal-insulator-semiconductor structure associated with the depletion region;

(e) a current blocking layer between the substrate and the active layer, wherein the current blocking layer has an opening for an electrical current;

(f) a front ohmic contact adjacent to the Schottky contact or the metal-insulator-semiconductor structure;

and wherein the front ohmic contact and the Schottky contact or the metal-insulator-semiconductor structure are positioned to regulate an electric current through the front ohmic contact to the back ohmic contact with a voltage applied across the front ohmic contact and the Schottky contact or the metal-insulator-semiconductor structure.

2. An electronic device according to claim 1 wherein the electron concentration of the active layer is less than 10¹⁶ cm⁻

3.

3. An electronic device according to claim 1 wherein the oxygen concentration of the active layer is less than 10¹⁶ cm⁻

3.

4. An electronic device according to claim 1 and further comprising a transition layer between the substrate and the active layer wherein said transition layer is deposited by vapor phase epitaxy and comprises Ga_1-x3-y3Al_x3In_y3N (0≦

x3≦

1, 0≦

y3≦

1).

5. An electronic device according to claim 4 wherein the oxygen concentration of the active layer is less than 10¹⁶ cm⁻

3.

6. An electronic device according to claim 4 wherein the electron concentration of the active layer is less than 10¹⁶ cm⁻

3.

7. An electronic device according to claim 4 wherein the depletion region extends into the transition layer.

8. An electronic device according to claim 4 wherein the transition layer has an impurity concentration or alloy composition that varies along a growth direction so that lattice matching is realized at an interface between the substrate and the transition layer and at an interface between the transition layer and the active layer.

9. An electronic device according to claim 4 wherein the transition layer is sufficiently thick to bury cracks created at an interface between the substrate and the transition layer.

10. An electronic device according to claim 4 wherein the transition layer is doped with an impurity which prevents diffusion of impurities contained in the substrate.

11. An electronic device according to claim 1 wherein the substrate is made of a wafer fabricated from a bulk crystal of Ga_1-x1-y1Al_x1In_y1N (0≦

x1≦

1, 0≦

y1≦

1) grown in supercritical ammonia.

12. An electronic device according to claim 1 wherein the substrate contains sodium at a concentration of greater than about 10¹⁶ cm⁻

3 and the active layer has a sodium concentration at least 100 times less than the sodium concentration of the substrate.

13. An electronic device according to claim 1 wherein the active layer is grown by vapor phase epitaxy.

14. An electronic device according to claim 1 wherein the substrate is a c plane wafer with miscut more than 0.1 degree and less than 5 degrees.

15. An electronic device according to claim 1 wherein the current blocking layer comprises silicon dioxide.

16. An electronic device according to claim 1 wherein the current blocking layer comprises a gas.

17. An electronic device according to claim 16 wherein the gas is air.

18. An electronic device according to claim 1 wherein the current blocking layer comprises p-type or semi-insulating Ga_1-x-yAl_xIn_yN (0≦

x≦

1, 0≦

y≦

1).

19. An electronic device according to claim 1 further comprising a region of high electron concentration underneath the front ohmic contact.

20. An electronic device according to claim 1 wherein the depletion region has a p-n junction associated with the depletion region and further comprising an additional n-type semiconductor on the p-n junction to form a bipolar transistor.

21. An electronic device according to claim 1 wherein x1=x2=0 and y1=y2=0.