Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same

• US 9,305,782 B2
• Filed: 10/06/2014
• Issued: 04/05/2016
• Est. Priority Date: 07/10/2006
• Status: Active Grant

• Current Assignee: Lodestar Licensing Group LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Zhou, Baosuo, Abatchev, Mirzafer K., Niroomand, Ardavan, Morgan, Paul A., Meng, Shuang, Greely, Joseph Neil, Coppa, Brian J.
• Primary Examiner(s): RAYMOND, BRITTANY L
• Application Number:
  US14/507,507
• Publication Number:
  US 20150021744A1
• Time in Patent Office: 547 Days
• Field of Search: 430/9, 430/311, 430/313, 257/E21.035, 257/E21.038, 257/E21.039
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0335 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Claims

1. An in process semiconductor device, comprising:

an etch mask above a layer to be etched, the etch mask comprising a plurality of triads of spacers on the outermost surface of the layer to be etched, the triads comprising the first spacer bracketed by second spacers on the surface with each of the spacers within the triad having a different elevational thickness and the second spacers contacting the first spacer, wherein the first spacer has an elevational thickness greater than either of the bracketing second spacers.

2. The in process semiconductor device of claim 1 wherein at least one of the spacers comprises silicon nitride.

3. The in process semiconductor device of claim 1 wherein each of the spacers are formed from one of two different types of materials.

4. The in process semiconductor device of claim 1 wherein the at least two spacers are adjacent spacers comprising different materials.

5. An in process semiconductor device comprising:

an etch mask above a layer to be etched, the etch mask comprising a plurality of groups of five adjacent spacers of the layer to be etched, each group comprising triads of spacers on the outermost surface, the triads comprising the first spacer bracketed by second spacers on the surface with each of the spacers within the triad having a different elevational thickness and the second spacers contacting the first spacer, wherein the first spacer has an elevational thickness greater than either of the bracketing second spacers.

6. The in process semiconductor device of claim 5 wherein all of the spacers are non-planar.

7. The in process semiconductor device of claim 5 wherein at least one of the spacers comprise silicon nitride.

8. The in process semiconductor device of claim 5 wherein each spacer within the group of five spacers has a different elevational thickness.

9. The in process semiconductor device of claim 5 wherein the groups of five spacers are spaced apart from one another.

10. The in process semiconductor device of claim 5 wherein individual spacers within the groups of five spacers contact one another.