Method of making a three dimensional NAND device

• US 9,305,849 B1
• Filed: 11/12/2014
• Issued: 04/05/2016
• Est. Priority Date: 11/12/2014
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Fujino, Shigehiro, Koka, Sateesh, Kanakamedala, Senaka, Zhang, Yanli, Makala, Raghuveer S., Sharangpani, Rahul, Matamis, George, Zhao, Wei, Tsutsumi, Masanori
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): Budd, Paul
• Application Number:
  US14/539,372
• Time in Patent Office: 510 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A monolithic three dimensional NAND string includes a semiconductor channel, an end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, a charge storage material layer located between the plurality of control gate electrodes and the semiconductor channel, a tunnel dielectric located between the charge storage material layer and the semiconductor channel, and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. Each of the plurality of control gate electrodes are located at least partially in an opening in the clam-shaped blocking dielectric, and a plurality of discrete cover oxide segments embedded in part of a thickness of the charge storage material layer and located between the blocking dielectric and the charge storage material layer.

Claims

1. A method of making a monolithic three dimensional NAND string, comprising:

forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, the first material layers comprising a sacrificial material and the second material layers comprising an electrically insulating material;

forming at least one front side opening in the stack;

forming a charge storage material layer in the at least one front side opening;

forming a tunnel dielectric over the charge storage material layer in the at least one front side opening;

forming a semiconductor channel over the tunnel dielectric in the at least one front side opening;

forming a back side opening in the stack;

selectively removing the first material layers without removing the second material layers through the back side opening, thereby forming back side recesses between adjacent second material layers, wherein the portions of the charge storage material layer on exposed in the back side recesses;

selectively oxidizing portions of the charge storage material layer exposed in the back side recesses partially through a thickness of the charge storage material layer to form a cover oxide segments in the charge storage material layer;

forming a blocking dielectric over a sidewall in the back side opening, over exposed surfaces of the second material layers and over the cover oxide segments in the back side recesses, the blocking dielectric having a clam-shaped portion in the back side recesses; and

forming a plurality of control gate electrodes, each of the plurality of control gate electrodes is located at least partially in an opening in the respective clam-shaped portion of the blocking dielectric.

2. The method of claim 1, wherein a portion of the charge storage material layer remains between each cover oxide segment and the tunneling dielectric.

3. The method of claim 1, wherein the first material layers comprise silicon nitride, the charge storage material layer comprises silicon nitride, and the second material layers comprise silicon oxide.

4. The method of claim 3, wherein selectively oxidizing portions of the charge storage material layer comprises performing an in-situ steam generated (ISSG) oxidation or a steam low pressure radical oxidation in a batch furnace of an outer portion of the silicon nitride charge storage material layer.

5. The method of claim 4, further comprising forming a bather layer over the blocking dielectric in the back side recesses prior to forming the control gate electrodes, wherein the blocking dielectric comprises Al₂O₃, the control gate electrodes comprise tungsten and the barrier layer comprises TiN.

6. The method of claim 1, wherein the semiconductor channel comprises a hollow cylinder and further comprising filling the hollow cylinder with an insulating fill material.

7. The method of claim 1, further comprising forming an insulating layer on the substrate prior to forming the stack of first and second material layers.

8. The method of claim 1, further comprising:

forming a semiconductor liner over the tunnel dielectric;

etching a bottom surface of the semiconductor liner, the charge storage material layer and the tunnel dielectric to expose a portion of the substrate in the front side opening; and

forming the semiconductor channel over the semiconductor liner in contact with the exposed portion of the substrate in the front side opening.

9. The method of claim 1, further comprising:

forming at least one etch stop layer in the at least one front side opening prior to forming the charge storage material layer; and

selectively removing exposed portions of the at least one etch stop layer in the back side recesses to expose portions of the charge storage material layer in the back side recesses after the step of selectively removing the first material layers.

10. The method of claim 1, wherein:

the substrate comprises a silicon substrate;

the monolithic three dimensional NAND string is located in an array of monolithic three dimensional NAND strings over the silicon substrate; and

at least one memory cell in the first device level of the three dimensional array of NAND strings is located over another memory cell in the second device level of the three dimensional array of NAND strings.

11. The method of claim 10, wherein the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon.