Through silicon via (TSV) isolation structures for noise reduction in 3D integrated circuit

• US 9,305,864 B2
• Filed: 09/12/2013
• Issued: 04/05/2016
• Est. Priority Date: 12/13/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Horng, Jaw-Juinn, Yu, Chia-Lin, Chen, Chung-Hui, Yeh, Der-Chyang, Peng, Yung-Chow
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): ESKRIDGE, CORY W
• Application Number:
  US14/024,925
• Publication Number:
  US 20140008817A1
• Time in Patent Office: 936 Days
• Field of Search: 257/276, 257/621, 257/698, 257/E23.067, 257/341, 257/401, 257/774, 438/667
• US Class Current: 1/1
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Through silicon via (TSV) isolation structures are provided and suppress electrical noise such as may be propagated through a semiconductor substrate when caused by a signal carrying active TSV such as used in 3D integrated circuit packaging. The isolation TSV structures are surrounded by an oxide liner and surrounding dopant impurity regions. The surrounding dopant impurity regions may be P-type dopant impurity regions that are coupled to ground or N-type dopant impurity regions that may advantageously be coupled to V_DD. The TSV isolation structure is advantageously disposed between an active, signal carrying TSV and active semiconductor devices and the TSV isolation structures may be formed in an array that isolates an active, signal carrying TSV structure from active semiconductor devices.

Claims

1. A semiconductor device comprising:

an active semiconductor device formed on a surface of a semiconductor substrate;

an isolation through silicon via (TSV) extending through said semiconductor substrate and laterally spaced from said active semiconductor device and next to a surface dopant impurity region of a first dopant impurity type disposed in said surface between said isolation TSV and said active semiconductor device, said surface dopant impurity region having a dopant concentration different from said substrate; and

said isolation TSV surrounded laterally by a surrounding dopant impurity region along part of a length of said isolation TSV, wherein said surrounding dopant impurity region extends from said surface to a termination location above a bottom surface of said semiconductor substrate.

2. The semiconductor device as in claim 1, wherein said surrounding dopant impurity region is one of a P-type dopant impurity region and an N-type dopant impurity region.

3. The semiconductor device as in claim 1, further including an oxide liner laterally surrounding said isolation TSV, wherein said surrounding dopant impurity region surrounds said oxide liner along a part of a length of said oxide liner.

4. The semiconductor device as in claim 1, further comprising an active TSV containing a conductive line carrying a signal and extending through said semiconductor substrate, said isolation TSV interposed between said active TSV and said active semiconductor device and wherein said active semiconductor device comprises a transistor.

5. The semiconductor device as in claim 4, further comprising a plurality of further isolation TSVs forming an array, said active TSV surrounded by said array and isolated from said transistor by said array.

6. The semiconductor device as in claim 4, wherein said active TSV includes an oxide liner formed on sidewalls thereof and a surrounding dopant impurity region that laterally surrounds said oxide liner.

7. The semiconductor device as in claim 1, wherein said first dopant impurity type comprises P-type, said surrounding dopant impurity region comprises said P-type dopant impurity region coupled to ground and overlaps with said surface dopant impurity region of said first dopant impurity type, and said isolation TSV contains a copper lead therein.

8. The semiconductor device as in claim 1, wherein said first dopant impurity type comprises N-type and said surrounding dopant impurity region comprises said N-type dopant impurity region coupled to V_DD.

9. The semiconductor device as in claim 8, wherein said surrounding dopant impurity region overlaps with said surface dopant impurity region of said first dopant impurity type, said semiconductor substrate comprises a P-type material, said isolation TSV is coupled to V_DD through said surface dopant impurity which is coupled to V_DD, and said isolation TSV contains a copper lead therein.

10. The semiconductor device as in claim 1, wherein said isolation TSV is a P-type isolation TSV with said surrounding dopant impurity region comprising said P-type dopant impurity region coupled to ground and said first dopant impurity type comprising P-type and further comprising:

a plurality of further of said P-type isolation TSVs and a plurality of N-type isolation TSVs, each said N-type isolation TSV having said surrounding dopant impurity region being an N-type dopant impurity region disposed next to a further N-type dopant impurity region and coupled to V_DD;

an active TSV structure containing a conductive lead, carrying a signal and extending through said substrate, and

wherein said active TSV structure is surrounded by an array of said N-type isolation TSVs and said array of N-type isolation TSVs is surrounded by an array of said P-type isolation TSVs.

11. A semiconductor device comprising:

an active semiconductor device formed on a surface of a semiconductor substrate;

an isolation through silicon via (TSV) extending through said semiconductor substrate, said isolation TSV laterally spaced front said active semiconductor device;

a surface dopant impurity region of a first dopant impurity type disposed in said surface between said isolation TSV and said active semiconductor device, said surface dopant impurity region haying a dopant concentration different from said substrate;

an oxide liner laterally surrounding said isolation TSV; and

a surrounding dopant impurity region laterally surrounding the oxide liner along a part of a length of the oxide liner, wherein said surrounding dopant impurity region extends from said surface to a termination location above a bottom surface of said semiconductor substrate.

12. The semiconductor device of claim 11, further comprising an active TSV containing a conductive line carrying a signal and extending through said semiconductor substrate, said isolation TSV interposed between said active TSV and said active semiconductor device and wherein said active semiconductor device comprises a transistor.

13. The semiconductor device as in claim 12, further comprising a plurality of further isolation TSVs forming an array, said active TSV surrounded by said array and isolated from said transistor by said array.

14. The semiconductor device as in claim 12, wherein said active TSV includes an oxide liner formed on sidewalls thereof and a surrounding dopant impurity region that laterally surrounds said oxide liner.

15. The semiconductor device as in claim 11, wherein said first dopant impurity type comprises P-type, said surrounding dopant impurity region comprises said P-type dopant impurity region coupled to ground and overlaps with said surface dopant impurity region of said first dopant impurity type, and said isolation TSV contains a copper lead therein.

16. The semiconductor device as in claim 11, wherein:

said first dopant impurity type comprises N-type and said surrounding dopant impurity region comprises said N-type dopant impurity region coupled to VDD, and

said surrounding dopant impurity region overlaps with said surface dopant impurity region of said first dopant impurity type, said semiconductor substrate comprises a P-type material, said isolation TSV is coupled to VDD through said surface dopant impurity which is coupled to VDD, and said isolation TSV contains a copper lead therein.

17. The semiconductor device as in claim 11, wherein said isolation TSV is a P-type isolation TSV with said surrounding dopant impurity region comprising said P-type dopant impurity region coupled to ground and said first dopant impurity type comprising P-type and further comprising:

a plurality of further of said P-type isolation TSVs and a plurality of N-type isolation TSVs, each said N-type isolation TSV having said surrounding dopant impurity region being an N-type dopant impurity region disposed next to a further N-type dopant impurity region and coupled to V_DD;

an active TSV structure containing a conductive lead, carrying a signal and extending through said substrate, and

wherein said active TSV structure is surrounded by an array of said N-type isolation TSVs and said array of N-type isolation TSVs is surrounded by an array of said P-type isolation TSVs.

18. A semiconductor device comprising:

an active semiconductor device formed on a surface of a semiconductor substrate;

an isolation through silicon via (TSV) extending through said semiconductor substrate, said isolation TSV laterally spaced from said active semiconductor device;

a surface dopant impurity region of a first dopant impurity type disposed in said surface between said isolation TSV and said active semiconductor device, said surface dopant impurity region having a dopant concentration different from said substrate;

an oxide liner laterally surrounding said isolation TSV, and extending from the surface to a bottom surface of the semiconductor substrate; and

a surrounding dopant impurity region laterally surrounding the oxide liner along a part of a length of the oxide liner, wherein said surrounding dopant impurity region extends from said surface to a termination location above the bottom surface of said semiconductor substrate.

19. The semiconductor device of claim 18, wherein the surface dopant impurity region extends from said surface to a termination location above the termination location of the surrounding dopant impurity region.

20. The semiconductor device of claim 19, wherein said surrounding dopant impurity region comprises a P-type dopant impurity region coupled to ground and said first dopant impurity type comprises P-type, the device further comprising:

a plurality of additional ones of said isolation TSVs;

an active TSV structure containing a conductive lead, carrying a signal and extending through said substrate,

wherein said isolation TSV and said plurality of additional isolation TSVs are located between the active semiconductor device and the active TSV structure.