Devices, systems and methods for manufacturing through-substrate vias and front-side structures

• US 9,305,865 B2
• Filed: 10/31/2013
• Issued: 04/05/2016
• Est. Priority Date: 10/31/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jindal, Anurag, He, Jian, Vasudevan, Lalapet Rangan, Kirby, Kyle K., Li, Hongqi
• Primary Examiner(s): Movva, Amar
• Assistant Examiner(s): Maruf, Sheikh
• Application Number:
  US14/068,837
• Publication Number:
  US 20150115445A1
• Time in Patent Office: 887 Days
• Field of Search: 438/667, 438/637, 257/741, 257770-774, 257/E21.507, 257/E23.011
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Methods of manufacturing semiconductor devices and semiconductor devices with through-substrate vias (TSVs). One embodiment of a method of manufacturing a semiconductor device includes forming an opening through a dielectric structure and at least a portion of a semiconductor substrate, and forming a dielectric liner material having a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening. The method further includes removing the conductive material such that the second portion of the dielectric liner material is exposed, and forming a damascene conductive line in the second portion of the dielectric liner material that is electrically coupled to the TSV.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming an opening through a dielectric structure and through at least a portion of a semiconductor substrate under the dielectric structure, wherein the opening is configured to receive material for a through-substrate via (TSV);

forming a dielectric liner material such that the dielectric liner material has a first portion lining the opening and a second portion on an outer surface of the dielectric structure laterally outside of the opening;

depositing a conductive material such that a first portion of the conductive material is in the opening and a second portion of the conductive material is on an exposed surface of the second portion of the dielectric liner material laterally outside of the opening;

removing the second portion of the conductive material such that the second portion of the dielectric liner material is exposed, wherein at least a portion of the second portion of the dielectric liner material remains on the dielectric structure and a substantial portion of the first portion of the conductive material remains in the opening such that the remaining portion of the first portion of the conductive material defines a TSV; and

forming a damascene conductive line in the dielectric liner material, wherein the damascene line extends through the dielectric liner material over the dielectric structure laterally with respect to the TSV.

2. The method of claim 1 wherein the damascene conductive line is formed within the dielectric liner material such that damascene line and dielectric liner material have equal thicknesses.

3. The method of claim 1 wherein forming the dielectric liner material comprises depositing an undoped oxide onto the dielectric structure.

4. The method of claim 1 wherein removing the second portion of the conductive material comprises performing a chemical-mechanical removal procedure that stops on or at a depth in, but not completely through, the dielectric liner material.

5. The method of claim 1 wherein the second portion of the dielectric liner material is a permanent layer in the semiconductor die.

6. The method of claim 1, wherein after removing the second portion of the conductive material, the method further comprises annealing the first portion of the conductive material and subsequently removing a portion of the annealed first portion of the conductive material and a barrier/seed structure such that the second portion of the dielectric liner material is exposed.

7. The method of claim 1 wherein forming the damascene line comprises forming a trench in the dielectric liner material at least generally aligned with the TSV and extending laterally from the TSV, depositing a conductive material into the trench, and removing an overburden portion of the conductive material deposited into the trench, and wherein a thickness of the dielectric liner material remains on the outer surface of the dielectric structure after removing the overburden portion of the conductive material deposited into the trench.

8. The method of claim 7, further comprising forming a second trench in the second portion of the dielectric liner material over a contact spaced laterally apart from the TSV, and forming a second damascene line in the second trench.

9. The method of claim 1 wherein:

forming the dielectric liner material comprises depositing an undoped oxide onto the dielectric structure;

removing the second portion of the conductive material comprises performing a chemical-mechanical removal procedure that stops on or at a depth in, but not completely through, the dielectric liner material;

forming the damascene line comprises forming a trench in the dielectric liner material at least generally aligned with the TSV, depositing a conductive material into the trench, and removing an overburden portion of the conductive material deposited into the trench, and wherein a thickness of the dielectric liner material remains on the outer surface of the dielectric structure after removing the overburden portion of the conductive material deposited into the trench.

10. The method of claim 1, wherein before forming the damascene conductive line, the method further comprises:

depositing an additional damascene dielectric material on the second portion of the dielectric liner;

forming an opening through the damascene dielectric material and the second portion of the dielectric liner, wherein the opening is aligned with the TSV; and

depositing a conductive material in the opening through the damascene dielectric material and the second portion of the dielectric liner.

11. A method of manufacturing a semiconductor device having a semiconductor substrate, solid-state feature formed on the substrate, an dielectric structure on the semiconductor substrate and over the solid-state feature, and a contact extending through the dielectric structure and electrically coupled to the contact, the method comprising:

forming a through-substrate via (TSV) opening extending through the dielectric structure and at least partially through the semiconductor substrate, wherein the TSV opening is spaced laterally apart from the contact;

forming a continuous dielectric liner material in the TSV opening and on an outer surface of the dielectric structure such that the dielectric liner material has a portion superimposed over the contact;

depositing TSV material onto the dielectric liner material such that the TSV material at least partially fills the TSV opening and covers the portion of the dielectric liner material that is superimposed over the contact;

removing a portion of the TSV material until the portion of the dielectric liner material superimposed over the contact is exposed and a remaining portion of the TSV material resides in the TSV opening, wherein the remaining portion of the TSV material defines a TSV;

patterning trenches in the dielectric liner material including a first trench that exposes the contact and a second trench aligned with the TSV, wherein the first and second trenches extend over the dielectric structure laterally with respect to the contact and the TSV, respectively; and

filling the first and second trenches with a conductive material thereby forming first and second conductive lines that extend over the dielectric structure with respect to the contact and the TSV, respectively.

12. The method of claim 11 wherein forming the continuous dielectric liner material comprises depositing a permanent dielectric material such that a first portion of the dielectric liner lines the TSV opening and second portion of the dielectric liner material covers the dielectric structure.

13. The method of claim 12 wherein depositing the TSV material comprises depositing a bulk copper into the TSV opening and onto the second portion of the dielectric liner material, and removing a portion of the TSV material comprises a chemical-mechanical removal process that stops on or at depth in the dielectric liner material, but not completely through the dielectric liner material.

14. The method of claim 13 wherein the dielectric liner material comprises an undoped oxide.