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Low resistance replacement metal gate structure

  • US 9,305,923 B1
  • Filed: 12/02/2014
  • Issued: 04/05/2016
  • Est. Priority Date: 12/02/2014
  • Status: Expired due to Fees
First Claim
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1. A method of forming a semiconductor structure, said method comprising:

  • providing a structure comprising a first gate cavity of a first width and exposing a first portion of a semiconductor material portion and a second gate cavity of a second width that is greater than said first width and exposing a second portion of said semiconductor material portion, wherein a dielectric spacer surrounds said first and said second gate cavities;

    forming a material stack comprising, from bottom to top, a high k dielectric material layer and a metal nitride hard mask layer on exposed surfaces of said structure located inside and outside of said first and said second gate cavities;

    forming an amorphous-silicon cap over said material stack, wherein said amorphous-silicon cap has a first portion located on horizontal surfaces of said material stack having a first thickness and a second portion located on vertical surfaces of said material stack having a second thickness that is less than said first thickness;

    exposing inner sidewall surfaces of said dielectric spacer surrounding said first and said second gate cavities using said first portion of said amorphous-silicon cap as a mask;

    forming additional amorphous-silicon sealing said first gate cavity, but not said second gate cavity;

    removing said additional amorphous-silicon, remaining portions of said amorphous-silicon cap, and remaining portions of said metal nitride hard mask to expose remaining portions of said high k dielectric material layer located within an upper and lower portion of said first and said second gate cavities; and

    forming a gate structure comprises from bottom to top, a workfunction metal portion having a stair-like surface profile, a diffusion barrier portion, a metal structure and a dielectric cap on said remaining portions of said high k dielectric material layer located within said lower portion of said first and said second gate cavities, wherein during forming of said workfunction metal portion, said remaining portions of said high k dielectric material layer are removed from said upper portion of said first and said second gate cavities.

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