Low resistance replacement metal gate structure

• US 9,305,923 B1
• Filed: 12/02/2014
• Issued: 04/05/2016
• Est. Priority Date: 12/02/2014
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Ok, Injo, Pranatharthiharan, Balasubramanian, Surisetty, Charan Veera Venkata Satya
• Primary Examiner(s): Swanson, Walter H
• Application Number:
  US14/558,249
• Time in Patent Office: 490 Days
• Field of Search: 438/283
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28008 Making conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/31056 the removal being a selective chemical etching step, e.g. selective dry etching through a mask
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A first sacrificial gate structure of a first width and a second sacrificial gate structure of a second width greater than the first width are provided on a semiconductor material portion. A dielectric spacer and a planarizing dielectric material are provided surrounding each sacrificial gate structure. Each sacrificial gate structure is then removed forming gate cavities. A high k dielectric material, a metal nitride hard mask and a physical vapor deposited (PVD) amorphous-silicon cap are provided. Vertical portions of the metal nitride hard mask and the high k dielectric material are removed from a portion of each gate cavity. Additional PVD amorphous silicon is then deposited and then all amorphous silicon and remaining metal nitride hard mask portions are removed. A work function portion having a stair-like surface, a diffusion barrier portion, a conductive metal structure and a dielectric cap are then formed into to each of the gate cavities.

Claims

1. A method of forming a semiconductor structure, said method comprising:

providing a structure comprising a first gate cavity of a first width and exposing a first portion of a semiconductor material portion and a second gate cavity of a second width that is greater than said first width and exposing a second portion of said semiconductor material portion, wherein a dielectric spacer surrounds said first and said second gate cavities;

forming a material stack comprising, from bottom to top, a high k dielectric material layer and a metal nitride hard mask layer on exposed surfaces of said structure located inside and outside of said first and said second gate cavities;

forming an amorphous-silicon cap over said material stack, wherein said amorphous-silicon cap has a first portion located on horizontal surfaces of said material stack having a first thickness and a second portion located on vertical surfaces of said material stack having a second thickness that is less than said first thickness;

exposing inner sidewall surfaces of said dielectric spacer surrounding said first and said second gate cavities using said first portion of said amorphous-silicon cap as a mask;

forming additional amorphous-silicon sealing said first gate cavity, but not said second gate cavity;

removing said additional amorphous-silicon, remaining portions of said amorphous-silicon cap, and remaining portions of said metal nitride hard mask to expose remaining portions of said high k dielectric material layer located within an upper and lower portion of said first and said second gate cavities; and

forming a gate structure comprises from bottom to top, a workfunction metal portion having a stair-like surface profile, a diffusion barrier portion, a metal structure and a dielectric cap on said remaining portions of said high k dielectric material layer located within said lower portion of said first and said second gate cavities, wherein during forming of said workfunction metal portion, said remaining portions of said high k dielectric material layer are removed from said upper portion of said first and said second gate cavities.

2. The method of claim 1, wherein said semiconductor material portion is a semiconductor fin, and said semiconductor fin is formed by a method comprising:

providing a semiconductor substrate having an uppermost semiconductor material; and

patterning said uppermost semiconductor material.

3. The method of claim 1, wherein said providing said structure comprises:

forming a first sacrificial gate structure of said first width on said first portion of said semiconductor material portion, and a second sacrificial gate structure of said second width on said second portion of said semiconductor material portion;

forming said dielectric spacer on sidewall surfaces of said first and said second sacrificial gate structures;

forming a planarizing dielectric material on outer sidewall surfaces of said dielectric spacer and surrounding said first and said second sacrificial gate structures; and

removing said first and said second sacrificial gate structures by etching.

4. The method of claim 1, wherein said high k dielectric material layer has a dielectric constant that is greater than a dielectric constant of said dielectric spacers.

5. The method of claim 1, wherein said forming said amorphous-silicon cap comprises a physical vapor deposition process using an RF generated plasma.

6. The method of claim 1, wherein said exposing said inner sidewall surfaces of said dielectric spacer surrounding said first and said second gate cavities using said first portion of said amorphous-silicon cap as a mask comprises:

selectively removing said second portion of said amorphous-silicon cap utilizing a first ammonium etchant to expose an underlying vertical portion of said metal nitride hard mask layer;

selectively removing said exposed underlying vertical portion of said metal nitride hard mask layer using a second ammonium etchant to expose an underlying vertical portion of said high k dielectric material layer; and

selectively removing said exposed underlying vertical portion of said high k dielectric material layer utilizing an HF etchant.

7. The method of claim 1, wherein said forming said additional amorphous-silicon comprises a physical vapor deposition process using an RF generated plasma.

8. The method of claim 1, wherein said removing said additional amorphous-silicon, said remaining portions of said amorphous-silicon cap, and said remaining portions of said metal nitride hard mask layer comprises:

selectively etching said additional amorphous-silicon and said remaining portions of said amorphous-silicon cap utilizing a first ammonium etchant; and

selectively removing said remaining portions of said metal nitride hard mask layer by a second ammonium etchant.

9. The method of claim 1, wherein said workfunction metal portion having said stair-like surface profile of said gate structure is formed by an organic planarizing layer chamfering process, wherein during said organic planarizing layer chamfering process of said workfunction metal portion, said remaining portions of said high k dielectric material layer are removed from said first and said second gate cavities.

10. The method of claim 1, wherein said workfunction metal portion is selected from an n-type workfunction metal.

11. The method of claim 1, wherein said workfunction metal portion is selected from a p-type workfunction metal.