Zero cost NVM cell using high voltage devices in analog process

• US 9,305,931 B2
• Filed: 05/10/2012
• Issued: 04/05/2016
• Est. Priority Date: 05/10/2011
• Status: Active Grant

• Current Assignee: Jonker LLC
• Original Assignee: Jonker LLC
• Inventors: Liu, David K. Y.
• Primary Examiner(s): Toledo, Fernando L
• Assistant Examiner(s): Nguyen, Lawrence-Linh T
• Application Number:
  US13/468,417
• Publication Number:
  US 20120287715A1
• Time in Patent Office: 1,426 Days
• Field of Search: 365/185.15
• US Class Current: 1/1
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7883 charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/47 with a floating-gate layer also being used as part of the peripheral transistor
• CPC Class Codes: H10B 41/60 the control gate being a doped region, e.g. single-poly memory cell

Abstract

A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate and a drift region to impart a programming voltage. Programming is effectuated using a drain extension which can act to inject hot electrons. The cell can be operated as a one-time programmable (OTP) or multiple-time programmable (MTP) device. The fabrication of the cell relies on processing steps associated with high voltage devices, thus avoiding the need for additional masks, manufacturing steps, etc.

Claims

1. A programmable non-volatile device situated on a substrate comprising:

a floating gate configured to store non-volatile memory data for the device;

wherein said floating gate is comprised of a material that is also used as a gate for a separate high voltage transistor driver device also situated on the substrate;

a source region coupled to a first terminal; and

a drain region coupled to a second terminal; and

a drift region coupled to the drain region;

wherein the drift region overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said first terminal of said drain region and second terminal of said source region can be imparted to said floating gate through areal capacitive coupling;

further wherein at least some structures of the device, including said floating gate, source region, drain region and drift region are constructed during analog process manufacturing steps also used to make high voltage devices of an integrated circuit incorporating the programmable non-volatile device.

2. The device of claim 1 wherein the device is programmed using hot channel electrons.

3. The device of claim 1 wherein said drift region is configured with a notched portion.

4. The device of claim 3 wherein said notched portion includes an extension of said drain region that is adapted to enhance hot electron injection into said floating gate.

5. The device of claim 3 wherein said capacitive coupling is also caused by areal overlap between said drain region and floating gate.

6. The device of claim 1 wherein an oxide thickness under said floating gate is at least 100 angstroms.

7. The device of claim 1, wherein the device is part of an array of cells contained in a high voltage I/O driver region of an integrated circuit.

8. The device of claim 1 wherein the device is configured as a one-time programmable device.

9. The device of claim 1 wherein the device is configured as a multiple time programmable device.

10. The device of claim 7 wherein the integrated circuit includes a separate array of memory cells resulting from a logic process, which separate array of memory cells have floating gate oxides thinner than said floating gate of the device.

16. The device of claim 3 wherein said notched portion overlaps and extends past an extension of said drain region such that a first region has an areal capacitive coupling overlap with said floating gate, and a second region enhances hot electron injection along an edge portion of said floating gate.

17. The device of claim 3 wherein a first width of said notched portion is controlled by a first mask during manufacturing to be larger than a second width provided in a second mask for implanting said extension of said drain region.

11. A lateral diffused metal oxide semiconductor (LDMOS) structure comprising:

a floating gate adapted to store charge carriers representing a data value;

a source region coupled to a first terminal; and

a drain region coupled to a second terminal; and

a drift region coupled to the drain region, said drift region having a first portion which is overlapping at least a first areal portion of said floating gate and a second notched portion;

the LDMOS being situated in a high voltage driver region and adapted such that a voltage applied to said first terminal of said drain region and second terminal of said source region can be imparted to said floating gate through areal capacitive coupling;

wherein the LDMOS structure can function as a memory cell.

12. The structure of claim 11 wherein the drain region overlaps a second portion of said floating gate.

13. The structure of claim 11 wherein said drain region extends through said second notched portion of said drift region and is configured to enhance hot electron injection into an edge region of said floating gate.

18. The structure of claim 11 wherein said wherein the LDMOS structure memory cell is manufactured at least in part during a high voltage analog process.

19. The structure of claim 11 wherein said floating gate is made of a polysilicon material that part of gates of other logic devices or memory cells in areas other than said high voltage driver region.

20. The structure of claim 11 wherein a first width of said notched portion is controlled by a first mask during manufacturing to be larger than a second width provided in a second mask for implanting said drift region.

14. A lateral drift N-type metal oxide semiconductor (LDMOS) structure comprising:

a floating gate having no contacts to a voltage supply;

a source region coupled to a first terminal; and

a drain region coupled to a second terminal; and

a drift region coupled to the drain region, said drift region having a first portion which is overlapping at least a first areal portion of said floating gate and a second notched portion;

the LDMOS structure being situated in a high voltage driver region and adapted such that a voltage applied to said first terminal of said drain region and second terminal of said source region can be imparted to said floating gate through areal capacitive coupling;

wherein the LDMOS structure can function as a memory cell.

21. The structure of claim 14 wherein the LDMOS memory cell is manufactured at least in part during a high voltage analog process.

22. The structure of claim 14 wherein said floating gate of the LDMOS memory cell is made of a polysilicon material also used for gates of other logic devices or memory cells in areas other than said high voltage driver region.

15. A programmable non-volatile device situated in a high voltage circuit portion of a substrate comprising:

a floating gate configured to store non-volatile memory data for the device;

wherein said floating gate is comprised of a material that is also used as a gate for a high voltage transistor driver device also situated in the high voltage circuit portion of the substrate;

a source region coupled to a first terminal; and

a drain region coupled to a second terminal, said drain region having an extension which abuts at least a first edge of said floating gate; and

a drift region coupled to the drain region which overlaps a sufficient portion of said gate such that a programming voltage for the device applied to said first terminal of said drain region and second terminal of said source region can be imparted to said floating gate through areal capacitive coupling;

wherein said drain extension extends within a notched portion of said drift region;

further wherein said drain region can inject hot electrons along said first edge of said floating gate in response to said programming voltage;

and further wherein the programmable non-volatile device is manufactured at least in part during a high voltage analog process.

23. The device of claim 15 wherein said floating gate of the LDMOS memory cell is made of a polysilicon material also used for gates of other logic devices or memory cells in areas other than said high voltage driver region.