Methods of making three dimensional NAND devices

• US 9,305,932 B2
• Filed: 06/30/2014
• Issued: 04/05/2016
• Est. Priority Date: 06/30/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Kanakamedala, Senaka Krishna, Zhang, Yanli, Makala, Raghuveer S., Lee, Yao-Sheng, Alsmeier, Johann, Matamis, George
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): Han, Jonathan
• Application Number:
  US14/319,283
• Publication Number:
  US 20150380423A1
• Time in Patent Office: 645 Days
• Field of Search: 257/2, 257/5, 257/314, 257/E21.209, 257/324, 438/382
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02271 deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition H01L21/02266 takes precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region

Abstract

A method of making a monolithic three dimensional NAND string includes providing a first stack of alternating first material layers and second material layers over a major surface of a substrate. The first material layers include first silicon oxide layers, the second material layers include second silicon oxide layers, and the first silicon oxide layers have a different etch rate from the second silicon oxide when exposed to the same etching medium. The first stack includes a back side opening, a front side opening, and at least a portion of a floating gate layer, a tunnel dielectric and a semiconductor channel located in the front side opening. The method also includes selectively removing the first material layers through the back side opening to form back side control gate recesses between adjacent second material layers.

Claims

1. A method of making a monolithic three dimensional NAND string, comprising:

providing a first stack of alternating first material layers and second material layers over a major surface of a substrate, wherein;

the first material layers comprise first silicon oxide layers, the second material layers comprise second silicon oxide layers, and the first silicon oxide layers have a different etch rate from the second silicon oxide layers when exposed to the same etching medium; and

the first stack comprises a back side opening, a front side opening, and at least a portion of a floating gate layer, a tunnel dielectric and a semiconductor channel located in the front side opening;

selectively removing the first material layers through the back side opening to form back side control gate recesses between adjacent second material layers;

forming a blocking dielectric in the back side control gate recesses through the back side opening; and

forming a plurality of control gate electrodes over the blocking dielectric in the back side control gate recesses through the back side opening.

2. The method of claim 1, wherein providing the first stack comprises:

providing a second stack of alternating first sacrificial material layers and the first material layers over the major surface of the substrate;

forming the front side opening in the first stack;

forming the floating gate layer, the tunnel dielectric and the semiconductor channel in the front side opening;

forming the back side opening in the second stack;

selectively removing the first sacrificial material layers to form first back side recesses between adjacent first material layers and to expose portions of the floating gate layer in the first back side recesses;

oxidizing or removing the exposed portions of the floating gate layer such that remaining portions of the floating gate layer located adjacent to the first material layers to form discrete floating gate segments; and

filling the first back side recesses through the back side opening with the second material layers to form the first stack.

3. The method of claim 2, wherein the first sacrificial material layers comprise silicon nitride layers.

4. The method of claim 2, wherein the floating gate layer comprises a polysilicon floating gate layer, and the step of oxidizing or removing the exposed portions of the floating gate layer comprises oxidizing the exposed portions of the polysilicon floating gate layer to form silicon oxide regions between the discrete floating gate segments.

5. The method of claim 2, wherein the floating gate layer comprises a polysilicon, metal, metal nitride or metal silicide floating gate layer, and the step of oxidizing or removing the exposed portions of the floating gate layer comprises removing the exposed portions of the floating gate layer to form void regions between the discrete floating gate segments.

6. The method of claim 5, wherein the step of filling the first back side recesses through the back side opening with the second material layers further fills the respective void regions with the respective second material layers.

7. The method of claim 1, wherein providing the first stack comprises:

depositing the alternating first material layers and second material layers over the major surface of the substrate;

forming the front side opening in the first stack;

forming the floating gate layer, the tunnel dielectric and the semiconductor channel in the front side opening; and

forming the back side opening in the first stack.

8. The method of claim 7, further comprising:

selectively removing the second material layers through the back side opening to form second back side recesses between adjacent control gate electrodes and to expose portions of the floating gate layer in the second back side recesses;

oxidizing or removing the exposed portions of the floating gate layer such that remaining portions of the floating gate layer located adjacent to the control gate electrodes to form discrete floating gate segments; and

filling the second back side recesses through the back side opening with insulating material layers.

9. The method of claim 8, further comprising:

depositing a liner over the blocking dielectric in the back side control gate recesses prior to forming the plurality of control gate electrodes; and

removing the blocking dielectric and the liner from the back side opening thereby exposing a surface of the second material layers in the back side opening.

10. The method of claim 9, wherein the liner comprises WN or TiN and the control gate electrodes comprise W.

11. The method of claim 8, wherein the floating gate layer comprises a polysilicon floating gate layer, and the step of oxidizing or removing the exposed portions of the floating gate layer comprises oxidizing the exposed portions of the polysilicon floating gate layer to form silicon oxide regions between the discrete floating gate segments.

12. The method of claim 8, wherein the floating gate layer comprises a polysilicon, metal, metal nitride or metal silicide floating gate layer, and the step of oxidizing or removing the exposed portions of the floating gate layer comprises removing the exposed portions of the floating gate layer to form void regions between the discrete floating gate segments.

13. The method of claim 12, wherein the step of filling the second back side recesses through the back side opening with the insulating material layers further fills the respective void regions with the respective insulating material layers.

14. The method of claim 1, wherein the floating gate layer comprises a polysilicon layer, and further comprising siliciding portions of the polysilicon floating gate layer exposed in the back side control gate recesses prior to forming the blocking dielectric in the back side control gate recesses.

15. The method of claim 1, wherein the blocking dielectric comprises a plurality of clam shaped regions inside the back side control gate recesses, and the plurality of control gate electrodes are located in the plurality of claim shaped regions in the blocking dielectric.

16. The method of claim 1, wherein the first silicon oxide layers are deposited by CVD using a dichlorosilane (H₂SiCl₂) source, and the second silicon oxide layers are deposited by CVD using a disilane (Si₂F₆) source.

17. The method of claim 1, wherein the first silicon oxide layers are deposited by High Aspect Ratio Process (HARP) non-plasma based CVD using TEOS and ozone sources, and the second silicon oxide layers are deposited by high density plasma (HDP) CVD.

18. The method of claim 1, wherein the first silicon oxide layers comprise borosilicate glass or borophosphosilicate glass layers, and the second silicon oxide layers deposited from a TEOS source.

19. The method of claim 1, wherein:

the substrate comprises a silicon substrate;

the monolithic three dimensional NAND string is located in an array of monolithic three dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the three dimensional array of NAND strings is located over another memory cell in a second device level of the three dimensional array of NAND strings; and

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon.

20. The method of claim 1, wherein selectively removing the first material layers comprises selective etching using a HF:

H₂O in a 1;

5-15 ratio or a HF;

C₂H₄O₂ in a 1;

40-60 ratio wet etch chemistry.

21. A method of making a monolithic three dimensional NAND string, comprising:

forming a stack of alternating first material layers and second material layers over a substrate, wherein the second material is different from the first material;

etching the stack to form a front side opening in the stack;

forming a silicon floating gate layer in the front side opening;

forming a tunnel dielectric over the silicon floating gate layer in the front side opening; and

forming a semiconductor channel layer over the tunnel dielectric in the front side opening;

etching the stack to form a back side opening in the stack;

selectively removing the first material layers through the back side opening to form first back side recesses between the second material layers and to expose portions of the silicon floating gate layer in the first back side recesses;

forming a metal layer in the first back side recesses in contact with the exposed portions of the silicon floating gate layer;

reacting the metal layer with the exposed portions of the silicon floating gate to form discrete silicide floating gate segments;

forming a blocking dielectric in the first back side recesses through the back side opening;

forming a plurality of control gate electrodes over the blocking dielectric in the first back side recesses through the back side opening;

selectively removing the second material layers through the back side opening to form second back side recesses between adjacent control gate electrodes and to expose remaining silicon portions of the silicon floating gate layer in the second back side recesses;

oxidizing or removing the exposed remaining silicon portions of the silicon floating gate layer; and

filling the second back side recesses through the back side opening with insulating material layers.

22. The method of claim 21, further comprising:

depositing a liner over the blocking dielectric in the back side recesses prior to forming the plurality of control gate electrodes; and

removing the blocking dielectric and the liner from the back side opening thereby exposing a surface of the second material layers in the back side opening.

23. The method of claim 22, wherein the silicon floating gate layer comprises a polysilicon floating gate layer, the metal layer comprises a Ti, W, Co, Ni, Pd or Pt layer, the liner comprises WN or TiN, and the control gate electrodes comprise W.

24. The method of claim 21, wherein:

the substrate comprises a silicon substrate;

the monolithic three dimensional NAND string is located in an array of monolithic three dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the three dimensional array of NAND strings is located over another memory cell in a second device level of the three dimensional array of NAND strings; and

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon.