Bottom recess process for an outer blocking dielectric layer inside a memory opening

• US 9,305,937 B1
• Filed: 10/21/2014
• Issued: 04/05/2016
• Est. Priority Date: 10/21/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Tsutsumi, Masanori, Sasaki, Hiroshi, Ogawa, Hiroyuki, Sano, Michiaki, Yamaguchi, Kensuke, Shimabukuro, Seiji, Miyamoto, Masato
• Primary Examiner(s): Perkins, Pamela E
• Application Number:
  US14/519,733
• Publication Number:
  US 20160111439A1
• Time in Patent Office: 532 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/41 of a memory region comprising a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A method of minimizing an overetch or damage to a semiconductor surface underneath a memory opening is provided. A first blocking dielectric layer is formed in a memory opening through a stack of an alternating plurality of material layers and insulator layers. A sacrificial liner is formed over the first blocking dielectric layer. An opening is formed through a horizontal portion of the sacrificial liner. A horizontal portion of the first blocking dielectric layer at a bottom of the memory opening can be etched through the opening in the sacrificial liner. A semiconductor surface of the substrate can be physically exposed at a bottom of the memory opening with minimal overetch and/or surface damage. A second blocking dielectric layer can be formed, before or after formation of the sacrificial liner, to provide a multilayer blocking dielectric.

Claims

1. A method of fabricating a memory device, comprising:

forming a stack including an alternating plurality of material layers and insulator layers over a substrate;

forming a memory opening extending through the stack;

forming a first blocking dielectric layer in the memory opening and over the stack;

forming a second blocking dielectric layer on the first blocking dielectric layer;

forming a sacrificial liner over the first blocking dielectric layer, wherein the sacrificial liner is formed on the second blocking dielectric layer;

forming an opening through a horizontal portion of the sacrificial liner;

etching a horizontal portion of the first blocking dielectric layer at a bottom of the memory opening through the opening in the sacrificial liner, whereby a semiconductor surface of the substrate is physically exposed at a bottom of the memory opening;

removing the sacrificial liner without removing the first blocking dielectric layer after the semiconductor surface of the substrate is physically exposed; and

forming a memory material layer and a tunneling dielectric layer within the memory opening.

2. The method of claim 1, wherein the opening in the sacrificial liner is formed by an anisotropic etch process, and the horizontal portion of the first blocking dielectric layer is etched by another anisotropic etch process.

3. The method of claim 1, wherein the opening in the sacrificial liner is formed by an anisotropic etch process, and the horizontal portion of the first blocking dielectric layer is etched by an isotropic etch process.

4. The method of claim 1, further comprising forming an opening through a horizontal portion of the second blocking dielectric layer employing an anisotropic etch process.

5. The method of claim 1, further comprising forming an opening through a horizontal portion of the second blocking dielectric layer employing an isotropic etch process.

6. The method of claim 1, wherein:

the sacrificial liner is formed on the first blocking dielectric layer prior to etching the horizontal portion of the first blocking dielectric layer;

the sacrificial liner is anisotropically etched; and

a top surface of the horizontal portion of the first blocking dielectric layer is physically exposed after anisotropic etching of the sacrificial liner.

7. The method of claim 6, wherein a remaining vertical portion of the sacrificial liner is present on a vertical portion of the first blocking dielectric layer during etching of the horizontal portion of the first blocking dielectric layer.

8. The method of claim 1, wherein the sacrificial liner comprises silicon oxide, silicon nitride or silicon, and the first blocking dielectric layer comprises a dielectric metal oxide having a dielectric constant greater than 7.9.

9. The method of claim 8, wherein the first blocking dielectric layer comprises aluminum oxide.

10. The method of claim 1, wherein the memory material layer comprises a charge trapping material or a floating gate material.

11. The method of claim 1, further comprising forming a semiconductor channel within the memory opening, the semiconductor channel contacting the semiconductor surface and vertically extending to a topmost material layer within the stack.

12. The method of claim 1, further comprising removing the material layers from the stack to form a plurality of recesses and forming a plurality of electrically conductive layers in the respective plurality of recesses.

13. The method of claim 12, further comprising forming a device on the substrate, wherein:

the device comprises a vertical NAND device; and

at least one of the electrically conductive layers in the stack comprises, or is electrically connected to, a word line of the vertical NAND device.

14. The method of claim 13, wherein:

the NAND device comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level;

the electrically conductive layers in the stack comprise, or are in electrical contact with, the plurality of control gate electrodes and extends from the device region to a contact region containing the plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

15. A method of fabricating a memory device, comprising:

forming a stack including an alternating plurality of material layers and insulator layers over a substrate;

forming a memory opening extending through the stack;

forming a first blocking dielectric layer in the memory opening and over the stack;

forming a sacrificial liner over the first blocking dielectric layer;

forming an opening through a horizontal portion of the sacrificial liner;

etching a horizontal portion of the first blocking dielectric layer at a bottom of the memory opening through the opening in the sacrificial liner, whereby a semiconductor surface of the substrate is physically exposed at a bottom of the memory opening;

removing the sacrificial liner without removing the first blocking dielectric layer after the semiconductor surface of the substrate is physically exposed;

forming a second blocking dielectric layer on the first blocking dielectric layer after removal of the sacrificial liner; and

forming a memory material layer and a tunneling dielectric layer within the memory opening.

16. The method of claim 15, further comprising forming an opening through a horizontal portion of the second blocking dielectric layer employing an anisotropic etch process.

17. The method of claim 15, further comprising forming an opening through a horizontal portion of the second blocking dielectric layer employing an isotropic etch process.

18. The method of claim 15, wherein the opening in the sacrificial liner is formed by an anisotropic etch process, and the horizontal portion of the first blocking dielectric layer is etched by another anisotropic etch process.

19. The method of claim 15, wherein the opening in the sacrificial liner is formed by an anisotropic etch process, and the horizontal portion of the first blocking dielectric layer is etched by an isotropic etch process.

20. The method of claim 15, wherein:

the sacrificial liner is formed on the first blocking dielectric layer prior to etching the horizontal portion of the first blocking dielectric layer;

the sacrificial liner is anisotropically etched; and

a top surface of the horizontal portion of the first blocking dielectric layer is physically exposed after anisotropic etching of the sacrificial liner.

21. The method of claim 20, wherein a remaining vertical portion of the sacrificial liner is present on a vertical portion of the first blocking dielectric layer during etching of the horizontal portion of the first blocking dielectric layer.

22. The method of claim 15, wherein the sacrificial liner comprises silicon oxide, silicon nitride or silicon, and the first blocking dielectric layer comprises a dielectric metal oxide having a dielectric constant greater than 7.9.

23. The method of claim 22, wherein the first blocking dielectric layer comprises aluminum oxide.

24. The method of claim 23, further comprising forming a second silicon oxide blocking dielectric layer on the first blocking dielectric layer prior to forming the sacrificial liner or after removing the sacrificial liner, wherein the sacrificial liner comprises silicon nitride or amorphous silicon.

25. The method of claim 15, wherein the memory material layer comprises a charge trapping material or a floating gate material.

26. The method of claim 15, further comprising forming a semiconductor channel within the memory opening, the semiconductor channel contacting the semiconductor surface and vertically extending to a topmost material layer within the stack.

27. The method of claim 15, further comprising removing the material layers from the stack to form a plurality of recesses and forming a plurality of electrically conductive layers in the respective plurality of recesses.

28. The method of claim 27, further comprising forming a device on the substrate, wherein:

the device comprises a vertical NAND device; and

at least one of the electrically conductive layers in the stack comprises, or is electrically connected to, a word line of the vertical NAND device.

29. The method of claim 28, wherein:

the NAND device comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level;

the electrically conductive layers in the stack comprise, or are in electrical contact with, the plurality of control gate electrodes and extends from the device region to a contact region containing the plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

30. A method of fabricating a memory device, comprising:

forming a stack including an alternating plurality of material layers and insulator layers over a substrate;

forming a memory opening extending through the stack;

forming a first blocking dielectric layer in the memory opening and over the stack, wherein the first blocking dielectric layer comprises aluminum oxide;

forming a sacrificial liner over the first blocking dielectric layer, wherein the sacrificial liner comprises silicon oxide, silicon nitride or silicon, and the first blocking dielectric layer comprises a dielectric metal oxide having a dielectric constant greater than 7.9;

forming an opening through a horizontal portion of the sacrificial liner;

etching a horizontal portion of the first blocking dielectric layer at a bottom of the memory opening through the opening in the sacrificial liner, whereby a semiconductor surface of the substrate is physically exposed at a bottom of the memory opening;

removing the sacrificial liner without removing the first blocking dielectric layer after the semiconductor surface of the substrate is physically exposed;

forming a second silicon oxide blocking dielectric layer on the first blocking dielectric layer prior to forming the sacrificial liner or after removing the sacrificial liner, wherein the sacrificial liner comprises silicon nitride or amorphous silicon; and

forming a memory material layer and a tunneling dielectric layer within the memory opening.

31. The method of claim 30, wherein the opening in the sacrificial liner is formed by an anisotropic etch process, and the horizontal portion of the first blocking dielectric layer is etched by another anisotropic etch process.

32. The method of claim 30, wherein the opening in the sacrificial liner is formed by an anisotropic etch process, and the horizontal portion of the first blocking dielectric layer is etched by an isotropic etch process.

33. The method of claim 30, further comprising forming an opening through a horizontal portion of the second silicon oxide blocking dielectric layer employing an anisotropic etch process.

34. The method of claim 30, further comprising forming an opening through a horizontal portion of the second silicon oxide blocking dielectric layer employing an isotropic etch process.

35. The method of claim 30, wherein:

the sacrificial liner is formed on the first blocking dielectric layer prior to etching the horizontal portion of the first blocking dielectric layer;

the sacrificial liner is anisotropically etched; and

a top surface of the horizontal portion of the first blocking dielectric layer is physically exposed after anisotropic etching of the sacrificial liner.

36. The method of claim 35, wherein a remaining vertical portion of the sacrificial liner is present on a vertical portion of the first blocking dielectric layer during etching of the horizontal portion of the first blocking dielectric layer.

37. The method of claim 30, wherein the memory material layer comprises a charge trapping material or a floating gate material.

38. The method of claim 30, further comprising forming a semiconductor channel within the memory opening, the semiconductor channel contacting the semiconductor surface and vertically extending to a topmost material layer within the stack.

39. The method of claim 30, further comprising removing the material layers from the stack to form a plurality of recesses and forming a plurality of electrically conductive layers in the respective plurality of recesses.

40. The method of claim 39, further comprising forming a device on the substrate, wherein:

the device comprises a vertical NAND device; and

at least one of the electrically conductive layers in the stack comprises, or is electrically connected to, a word line of the vertical NAND device.

41. The method of claim 40, wherein:

the NAND device comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the semiconductor substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate;

the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level;

the electrically conductive layers in the stack comprise, or are in electrical contact with, the plurality of control gate electrodes and extends from the device region to a contact region containing the plurality of electrically conductive via connections; and

the substrate comprises a silicon substrate containing a driver circuit for the NAND device.

42. The method of claim 30, wherein forming the second silicon oxide blocking dielectric layer on the first blocking dielectric layer prior to forming the sacrificial liner or after removing the sacrificial liner comprises forming the second silicon oxide blocking dielectric layer on the first blocking dielectric layer prior to forming the sacrificial liner.

43. The method of claim 30, wherein forming the second silicon oxide blocking dielectric layer on the first blocking dielectric layer prior to forming the sacrificial liner or after removing the sacrificial liner comprises forming the second silicon oxide blocking dielectric layer on the first blocking dielectric layer after removing the sacrificial liner.

44. The method of claim 30, wherein the sacrificial liner comprises silicon nitride.

45. The method of claim 30, wherein the sacrificial liner comprises amorphous silicon.