Uniformly doped leakage current stopper to counter under channel leakage currents in bulk FinFET devices

• US 9,306,001 B1
• Filed: 04/14/2015
• Issued: 04/05/2016
• Est. Priority Date: 04/14/2015
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc., International Business Machines Corporation, STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: GlobalFoundries, Inc., International Business Machines Corporation, STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Cai, Xiuyu, Liu, Qing, Xie, Ruilong, Yeh, Chun-Chen
• Primary Examiner(s): Fourson, III, George
• Application Number:
  US14/685,745
• Time in Patent Office: 357 Days
• Field of Search: 257/400, 438/284, 438/294
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Embodiments are directed to a method of forming a leakage current stopper of a fin-type field effect transistor (FinFET). The method includes forming at least one fin having an active region, a non-active region and a channel region in the active region. The method further includes exposing a surface of the non-active region, wherein the exposed surface leads to a portion of the non-active region that is substantially underneath the channel region. The method further includes implanting dopants through the exposed surface of the non-active region to form the leakage current stopper region.

Claims

1. A method of forming a leakage current stopper region of a fin-type field effect transistor (FinFET), the method comprising:

forming at least one fin having an active region and a non-active region;

forming a channel region in the active region of the at least one fin;

exposing a surface of the non-active region of the at least one fin, the exposed surface leading to a portion of the non-active region that is substantially underneath the channel region; and

implanting dopants through the exposed surface of the non-active region of the at least one fin to form the leakage current stopper region.

2. The method of claim 1 further comprising forming a source region and a drain region in the active region of the at least one fin.

3. The method of claim 2, wherein the implanted dopants of the leakage current stopper region suppress a flow of leakage current from the source region through the leakage current stopper region into the channel region.

4. The method of claim 3, wherein the implanted dopants comprises carbon.

5. The method of claim 2, wherein the leakage current stopper region extends under the channel region.

6. The method of claim 2 further comprising:

forming a gate region around the channel region;

wherein the gate region controls a flow of current from the source region through the channel region into the channel region.

7. The method of claim 1, wherein the exposing of the surface of the non-active region comprises:

recessing a portion of the active region to expose a portion of the non-active region.

8. The method of claim 7, wherein the exposing of the surface of the non-active region further comprises:

recessing the portion of the non-active region to expose the surface of the non-active region.

9. The method of claim 7 further comprising:

during the implanting of the dopants, blocking the dopants from entering the recessed portion of the active region.

10. The method of claim 1, wherein the implanting of the dopants through the exposed surface of the non-active region results in a substantially uniform distribution of dopants in the leakage current stopper region.

11. The method of claim 1, wherein the implanting of the dopants through the exposed surface of the non-active region substantially prevents dopants from entering the active region of the at least one fin.

20. The FinFET of claim 1, wherein the leakage current stopper region comprises a substantially uniform distribution of the dopants.

12. A fin-type field effect transistor (FinFET) comprising:

at least one fin having an active region and a non-active region;

a channel region in the active region of the at least one fin;

a leakage current stopper region in the non-active region;

the leakage current stopper region formed by;

exposing a surface of the non-active region of the at least one fin, the exposed surface leading to a portion of the non-active region that is substantially underneath the channel region; and

implanting dopants through the exposed surface of the non-active region of the at least one fin to form the leakage current stopper region.

13. The FinFET of claim 12 further comprising:

a source region and a drain region in the active region of the at least one fin.

14. The FinFET of claim 13, wherein the implanted dopants of the leakage current stopper region suppress a flow of leakage current from the source region through the leakage current stopper region into the channel region.

15. The FinFET of claim 14, wherein the implanted dopants comprise carbon.

16. The FinFET of claim 13, wherein the leakage current stopper region extends under the channel region.

17. The FinFET of claim 13 further comprising:

a gate region around the channel region, wherein the gate region controls a flow of current from the source region through the channel region into the channel region.

18. The FinFET of claim 12, wherein the exposing of the surface of the non-active region comprises:

recessing a portion of the active region to expose a portion of the non-active region.

19. The FinFET of claim 18, wherein the exposing of the surface of the non-active region further comprises:

recessing the portion of the non-active region to expose the surface of the non-active region.