Semiconductor device having planar source electrode

• US 9,306,015 B2
• Filed: 12/09/2013
• Issued: 04/05/2016
• Est. Priority Date: 03/27/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Suk-Kyun, Park, Chan-Ho
• Primary Examiner(s): GORDON, MATTHEW E
• Application Number:
  US14/100,455
• Publication Number:
  US 20140291758A1
• Time in Patent Office: 848 Days
• Field of Search: 257/331
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A semiconductor device includes a channel layer on a substrate; cell trench patterns in the channel layer; and a source pattern on the cell trench patterns. The source pattern includes: grooves, each having inclined sidewalls and bottom that extends in a horizontal direction in a portion of the channel layer between the cell trench patterns, source regions at the inclined sidewalls of the grooves, source isolation regions at the bottoms of the grooves, and a source electrode at interior regions of the grooves and that has a planar upper surface.

Claims

1. A semiconductor device, comprising:

a channel layer on a substrate;

cell trench patterns and dummy trench patterns in the channel layer, each of the cell trench patterns including a cell shield pattern at a lower region of a cell trench, a cell gate pattern at a middle region of the cell trench, and a cell capping pattern at an upper region of the cell trench, and each of the dummy trench patterns including a dummy trench wider and deeper than the cell trench, a dummy shield pattern at a lower region of the dummy trench, a dummy gate pattern at a middle region of the dummy trench, and a dummy capping pattern at an upper region of the dummy trench;

a source electrode on the cell trench patterns filling grooves between the cell trench patterns or the cell trench patterns and the dummy trench patterns;

source isolation regions below bottom surfaces of the grooves;

source regions under inclined sidewalls of the grooves and extending below the bottom surfaces of the grooves; and

an interlayer insulating layer on the dummy trench patterns,

wherein an upper surface of the source electrode on the cell trench pattern is flat, and a level of the upper surface of the source electrode is at the same level as an upper surface of the interlayer insulating layer on the dummy trench patterns, and

wherein an impurity concentration of each source region is higher than that of each source isolation region.

2. The semiconductor device of claim 1, wherein the dummy trench patterns neighbor a portion of the cell trench patterns, and,

wherein an upper surface of the source electrode is at a same vertical position as an upper surface of the interlayer insulating layer, and

wherein each of the dummy trench patterns includes a dummy trench wider and deeper than the cell trench, a dummy shield pattern at a lower region of the dummy trench, a dummy gate pattern at a middle region of the dummy trench, and a dummy capping pattern at an upper region of the dummy trench.

3. The semiconductor device of claim 1, further comprising a gate pickup trench pattern in the channel layer,

wherein the gate pickup trench pattern includes a gate pickup trench wider and deeper than the cell trench, a gate pickup shield pattern at a lower region of the gate pickup trench, and a gate pickup pattern at an upper region of the gate pickup trench, and

an upper surface of the dummy capping pattern is at a same vertical position as an upper surface of the gate pickup pattern.

4. The semiconductor device of claim 2, further comprising a shield pickup trench pattern in the channel layer,

wherein the shield pickup trench pattern includes a shield pickup trench wider and deeper than the cell trench, a shield pickup pattern being positioned in the shield pickup trench, and

wherein the upper surface of the dummy capping pattern is at a same vertical position as an upper surface of the shield pickup pattern.