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Integrated circuits with nanowires and methods of manufacturing the same

  • US 9,306,019 B2
  • Filed: 08/12/2014
  • Issued: 04/05/2016
  • Est. Priority Date: 08/12/2014
  • Status: Active Grant
First Claim
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1. A method of manufacturing an integrated circuit comprising:

  • forming a layered fin overlying a substrate, wherein the layered fin comprises an SiGe layer and an Si layer, wherein the SiGe layer and the Si layer alternate along a height of the layered fin;

    forming a gate barrier layer overlying the layered fin and along a side of the layered fin;

    forming a dummy gate overlying the substrate and the layered fin such that the gate barrier layer is positioned between the dummy gate and the layered fin;

    forming a source and a drain that are in contact with the layered fin;

    removing the dummy gate to expose the SiGe layer and the Si layer;

    removing the gate barrier layer after removing the dummy gate;

    removing the Si layer to produce an SiGe nanowire;

    forming a high K dielectric layer encasing the SiGe nanowire between the source and the drain; and

    forming a replacement metal gate encasing the high K dielectric layer and the SiGe nanowire between the source and the drain.

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