Semiconductor device having dual work function gate structure and electronic device having the same
First Claim
1. A semiconductor device comprising:
- a body including a first junction region;
a pillar positioned over the body and including a vertical channel region and a second junction region over the vertical channel region;
a gate trench exposing side surfaces of the pillar;
a gate dielectric layer provided in the gate trench and over a side surface of the pillar; and
a gate electrode provided in the gate trench, wherein the gate dielectric layer is interposed between the gate electrode and the gate trench,wherein the gate electrode comprising;
a first work function liner over the vertical channel region and including an aluminum-containing metal nitride;
a second work function liner over the second junction region and including a silicon-containing non-metal material; and
an air gap positioned between the second work function liner and the second junction region.
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Accused Products
Abstract
A semiconductor device includes a body including a first junction region; a pillar positioned over the body, and including a vertical channel region and a second junction region over the vertical channel region; a gate trench exposing side surfaces of the pillar; a gate dielectric layer covering the gate trench; and a gate electrode embedded in the gate trench, with the gate dielectric layer interposed therebetween. The gate electrode includes a first work function liner overlapping with the vertical channel region, and including an aluminum-containing metal nitride; a second work function liner overlapping with the second junction region, and including a silicon-containing non-metal material; and an air gap positioned between the second work function liner and the second junction region.
39 Citations
20 Claims
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1. A semiconductor device comprising:
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a body including a first junction region; a pillar positioned over the body and including a vertical channel region and a second junction region over the vertical channel region; a gate trench exposing side surfaces of the pillar; a gate dielectric layer provided in the gate trench and over a side surface of the pillar; and a gate electrode provided in the gate trench, wherein the gate dielectric layer is interposed between the gate electrode and the gate trench, wherein the gate electrode comprising; a first work function liner over the vertical channel region and including an aluminum-containing metal nitride; a second work function liner over the second junction region and including a silicon-containing non-metal material; and an air gap positioned between the second work function liner and the second junction region. - View Dependent Claims (3, 4, 8, 9, 10, 11, 12)
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2. The semiconductor device according to claim further comprising:
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a bit line trench formed in the body; a bit line provided in the bit line trench and electrically coupled to the first junction region; a bit line capping layer covering a top surface and side surfaces of the bit line; and a memory element electrically coupled to the second junction region.
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5. The semiconductor device according to claim herein the gate electrode further comprises:
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a first low resistivity electrode provided over the first work function liner; and a second low resistivity electrode over the second work function liner. - View Dependent Claims (6, 7)
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13. A semiconductor device comprising:
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a body including a first junction region; a bit line trench formed in the body; a bit line provided in the bit line trench and electrically coupled to the first junction region; a bit line capping layer provided over a top surface and over side surfaces of the bit line; a pair of first and second pillars positioned over the body and including vertical channel regions and second junction regions over the vertical channel regions; a gate trench having main trench which exposes a space between the first pillar and the second pillar, and branch trenches which expose side surfaces of the first and second pillars; a pair of first and second gate electrodes provided over the side surfaces of the first and second pillars exposed by the branch trenches, respectively; and memory elements electrically coupled with the second junction regions, respectively, wherein each of the first and second gate electrodes comprising; a first work function liner over a side surface of the vertical channel region and including an aluminum-containing metal nitride; a second work function liner over a side surface of the second junction region and including a silicon-containing non-metal material; and an air gap positioned between the second work function liner and the second junction region. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification