Semiconductor configuration having reduced on-state resistance

• US 9,306,044 B2
• Filed: 12/02/2011
• Issued: 04/05/2016
• Est. Priority Date: 02/01/2011
• Status: Active Grant

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Qu, Ning, Goerlach, Alfred
• Primary Examiner(s): Le, Thao X
• Assistant Examiner(s): Ida, Geoffrey
• Application Number:
  US13/982,430
• Publication Number:
  US 20140021509A1
• Time in Patent Office: 1,586 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes

Abstract

A semiconductor configuration, which includes an epitaxial layer of the first conductivity type disposed on a highly doped substrate of first conductivity type; a layer of a second conductivity type introduced into the epitaxial layer; and a highly doped layer of the second conductivity type provided at the surface of the layer of the second conductivity type. Between the layer of the second conductivity type and the highly doped substrate of the first conductivity type, a plurality of Schottky contacts, which are in the floating state, are provided mutually in parallel in the area of the epitaxial layer.

Claims

1. A semiconductor configuration, comprising:

an epitaxial layer of a first conductivity type disposed on a highly doped substrate of the first conductivity type;

a layer of a second conductivity type introduced into the epitaxial layer;

a highly doped layer of the second conductivity type provided at a surface of the layer of the second conductivity type; and

a plurality of floating Schottky contact metal layers provided vertically stacked in at least one trench region and disposed mutually in parallel and parallel to the highly doped substrate, and configured between the layer of the second conductivity type and the highly doped substrate of the first conductivity type, wherein each floating Schottky contact metal layer is isolated from one another by at least one intervening dielectric layer, and wherein each floating Schottky contact metal layer at least laterally contacts the epitaxial layer of the first conductivity type to form a non-ohmic Schottky contact;

wherein, at the surface of the layer of the second conductivity type, a highly doped layer of the first conductivity type and a highly doped layer of the second conductivity type are provided, at least two trenches filled with doped polysilicon and covered with dielectric layers are introduced into the epitaxial layer, the dielectric layers forming bottoms of the trenches are dimensioned to be thicker than the dielectric layers at side walls of the trenches, and an alternating sequence of the floating Schottky contact metal layers and the at least one intervening dielectric layer is provided below the dielectric layer forming the bottom of the respective trench.

2. The semiconductor configuration as recited in claim 1, wherein the Schottky contact metal layer of the alternating sequence most proximate to the highly doped substrate of the first conductivity has a distance to the highly doped substrate of the first conductivity type.

3. The semiconductor configuration as recited in claim 1, wherein the floating Schottky contact metal layers each have a width, and the dielectric layers provided between the Schottky contact metal layers each have a width.

4. The semiconductor configuration as recited in claim 3, wherein, between adjacent trenches of the semiconductor configuration, a mesa region is present in each case, in which a field distribution is periodically repeated at a distance, for which it holds that:

D=D_sk+D_gap,

D_sk being the width of the floating Schottky contact metal layers, and D_gap being the width of the further dielectric layers.

5. The semiconductor configuration as recited in claim 4, wherein a voltage distribution in mesa regions is linear in each case.

6. The semiconductor configuration as recited in claim 1, wherein at least two trenches filled with a dielectric layer are introduced into the epitaxial layer, a distance of the dielectric layers from the highly doped substrate of the first conductivity type is smaller than a distance of the layer of the second conductivity type from the highly doped substrate of the first conductivity type, and an alternating sequence of the floating Schottky contact metal layers and the at least one intervening dielectric layer is provided in each case between (i) the dielectric layer forming the bottom of the respective trench and facing the highly doped substrate of the first conductivity type and (ii) the highly doped substrate of the first conductivity type.

7. The semiconductor configuration as recited in claim 1, wherein the Schottky contact metal layers which are disposed mutually in parallel, are located one of underneath a body diode of a DMOS transistor or underneath the body diode of an IGBT.

8. The semiconductor configuration as recited in claim 1, further comprising:

a solderable front-side metallization and a solderable rear-side metallization.

9. A rectifier of a motor vehicle generator, the rectifier including a semiconductor configuration including an epitaxial layer of a first conductivity type disposed on a highly doped substrate of the first conductivity type, a layer of a second conductivity type introduced into the epitaxial layer, a highly doped layer of the second conductivity type provided at a surface of the layer of the second conductivity type, and a plurality of floating Schottky contact metal layers provided vertically stacked in at least one trench region and disposed mutually in parallel and parallel to the highly doped substrate, and configured between the layer of the second conductivity type and the highly doped substrate of the first conductivity type, wherein each floating Schottky contact metal layer is isolated from one another by at least one intervening dielectric layer, and wherein each floating Schottky contact metal layer at least laterally contacts the epitaxial layer of the first conductivity type to form a non-ohmic Schottky contact, and wherein, at the surface of the layer of the second conductivity type, a highly doped layer of the first conductivity type and a highly doped layer of the second conductivity type are provided, at least two trenches filled with doped polysilicon and covered with dielectric layers are introduced into the epitaxial layer, the dielectric layers forming bottoms of the trenches are dimensioned to be thicker than the dielectric layers at side walls of the trenches, and an alternating sequence of the floating Schottky contact metal layers and the at least one intervening dielectric layer is provided below the dielectric layer forming the bottom of the respective trench.