Semiconductor device with trench-like feed-throughs

• US 9,306,056 B2
• Filed: 10/30/2009
• Issued: 04/05/2016
• Est. Priority Date: 10/30/2009
• Status: Active Grant

• Current Assignee: Vishay Siliconix
• Original Assignee: Vishay Siliconix
• Inventors: Pattanayak, Deva, Owyang, King, Kasem, Mohammed, Terrill, Kyle, Katraro, Reuven, Chen, Kuo-In, Choi, Calvin, Chen, Qufei, Wong, Ronald, Lui, Kam Hong, Xu, Robert
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): Han, Jonathan
• Application Number:
  US12/610,148
• Publication Number:
  US 20110101525A1
• Time in Patent Office: 2,349 Days
• Field of Search: 438/270, 257/330
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05 of an individual bonding area
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/06051 Bonding areas having different shapes
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13014 being circular or elliptic
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

Claims

1. A semiconductor device comprising:

an electrically conductive substrate layer;

a drain contact, wherein said substrate layer is separated from said drain contact by an intervening layer;

a plurality of gate trenches that extend into but not completely through said intervening layer, each of said gate trenches filled with a first filler material;

a plurality of source contact trenches that extend into but not completely through said intervening layer, each of said source contact trenches filled with a second filler material different from said first filler material, wherein said source contact trenches are interleaved between said gate trenches; and

a plurality of feed-through trenches that extend completely through said intervening layer to said substrate layer, each of said feed-through trenches filled with said second filler material and coupled to said drain contact, wherein said feed-through trenches are adjacent to each other under said drain contact and are not interleaved with said gate trenches and are not interleaved with said source contact trenches.

2. The semiconductor device of claim 1 wherein said first filler material comprises polysilicon and said second filler material comprises tungsten.

3. The semiconductor device of claim 1 wherein said feed-through trenches are each lined with a conformal coating that separates said second filler material from said intervening layer.

4. The semiconductor device of claim 3 wherein said conformal coating comprises material selected from the group consisting of:

titanium and titanium-nitride.

5. The semiconductor device of claim 3 wherein said conformal coating comprises a thickness of titanium of about 600 Angstroms and a thickness of titanium-nitride of about 200 Angstroms.

6. The semiconductor device of claim 1 wherein said device comprises a flip chip having a plurality of solder balls formed on a surface thereof, wherein said drain contact is coupled to at least one of said solder balls.

7. The semiconductor device of claim 1 wherein said feed-through trenches are non-uniformly distributed under said drain contact between said drain contact and said substrate layer, wherein said feed-through trenches are concentrated toward a source region of said device.

8. The semiconductor device of claim 1 wherein each trench in said plurality of feed-through trenches has a depth of approximately 8.7 microns at their shallowest points, a width of approximately 0.9 microns, and a pitch of approximately 1.7 microns.

9. The semiconductor device of claim 1 wherein said feed-through trenches are non-uniformly distributed under a solder ball coupled to said drain contact.

10. A flip chip semiconductor device comprising:

a plurality of solder balls comprising a solder ball coupled to a drain contact on a first surface of said device;

a first metal layer on a second surface of said device, said second surface opposite said first surface;

a substrate layer adjacent said first metal layer, wherein said substrate layer is separated from said drain contact by an intervening layer;

a plurality of gate trenches that extend into but not completely through said intervening layer, each of said gate trenches filled with a first filler material;

a plurality of source contact trenches that extend into but not completely through said intervening layer, each of said source contact trenches filled with a second filler material different from said first filler material, wherein said source contact trenches are interleaved between said gate trenches, and wherein said source contact trenches are in contact with a second metal layer but said gate trenches are isolated from said second metal layer; and

a plurality of feed-through trenches that extend completely through said intervening layer to said substrate layer, each of said feed-through trenches with said second filler material and coupled to said drain contact, wherein said feed-through trenches pass through said intervening layer and into said substrate layer, wherein said feed-through trenches are adjacent to each other under said drain contact and are not interleaved with said gate trenches and are not interleaved with said source contact trenches, and further wherein in operation said device comprises a circuit from a source contact through said intervening layer, said substrate layer, and said feed-through trenches to said drain contact.

11. The semiconductor device of claim 10 wherein said first filler material comprises polysilicon and said second filler material comprises tungsten.

12. The semiconductor device of claim 10 wherein said source contact trenches and said feed-through trenches are each lined with a conformal coating that separates said second filler material from said intervening layer.

13. The semiconductor device of claim 12 wherein said conformal coating comprises material selected from the group consisting of:

titanium and titanium-nitride.

14. The semiconductor device of claim 10 wherein said feed-through trenches are non-uniformly distributed under said drain contact between said drain contact and said substrate layer, wherein a greater concentration of said feed-through trenches is located toward said source contact.

15. The semiconductor device of claim 10 wherein said feed-through trenches are non-uniformly distributed under said solder ball.

16. A method of fabricating a flip chip, said method comprising:

forming a plurality of gate trenches in a surface of an epitaxial layer of a structure, said gate trenches extending partially into but not completely through said epitaxial layer, wherein a first plurality of source contact trenches are also formed in said surface of said epitaxial layer, said source gate trenches extending partially into but not completely through said epitaxial layer, said source contact trenches interleaved between said gate trenches;

forming a plurality of feed-through trenches in said surface, said feed-through trenches extending completely through said epitaxial layer and into a substrate layer adjoining a second surface of said epitaxial layer; and

depositing a first filler material into said source contact trenches and depositing a second filler material into both said gate trenches and said feed-through trenches, said second filler material different from said first filler material, wherein said gate trenches are subsequently electrically coupled to a first solder ball used as a source contact, wherein said feed-through trenches are adjacent to each other under a drain contact and are not interleaved with said gate trenches and are not interleaved with said source contact trenches, and wherein said feed-through trenches are subsequently electrically coupled to a second solder ball used as a drain contact.

17. The method of claim 16 wherein said first filler material comprises polysilicon and said second filler material comprises tungsten.

18. The method of claim 16 further comprising, in a same process step performed after said gate trenches and said feed-through trenches are formed and before said second filler material is deposited, depositing a conformal coating that lines said gate trenches and that lines said feed-through trenches.

19. The method of claim 18 wherein said conformal coating comprises material selected from the group consisting of:

titanium and titanium-nitride.

20. The method of claim 16 wherein said feed-through trenches are non-uniformly distributed within said drain region under said drain contact, wherein said feed-through trenches are concentrated toward a source region of said flip chip.

21. The method of claim 16 wherein said first filler material is deposited into said source contact trenches and into said feed-through trenches in a same process step.