Semiconductor device

• US 9,306,062 B2
• Filed: 09/23/2013
• Issued: 04/05/2016
• Est. Priority Date: 09/28/2012
• Status: Expired due to Fees

• Current Assignee: Ablic Inc. (Minebea Mitsumi, Inc.)
• Original Assignee: Seiko Instruments Incorporated (Seiko Group)
• Inventors: Kobayashi, Naoto
• Primary Examiner(s): Nguyen, Khiem D
• Assistant Examiner(s): Vu, Pauline
• Application Number:
  US14/033,892
• Publication Number:
  US 20140091387A1
• Time in Patent Office: 925 Days
• Field of Search: 257/330, 257/331
• US Class Current: 1/1
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device has a body layer disposed in a semiconductor substrate, cell regions arranged around a surface layer part of the body layer, and trenches arranged in a grid pattern for separating the cell regions from each other. A gate insulating film covers inner walls of the first trenches and an inner wall of the second trench, and a gate electrode is filled in the first trenches and the second trench covered by the gate insulating film. A cell circumferential region is disposed to surround an outer side of the second trench. An interlayer insulating film is disposed on the cell regions, the first trenches, and the second trench. A gate contact hole is disposed in the interlayer insulating film at an intersection of the first trenches arranged in the grid pattern. A gate wiring is connected to the gate electrode via the gate contact hole.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a body layer disposed in the semiconductor substrate;

a plurality of cell regions, each comprising a source region arranged around a surface layer part of the body layer;

first trenches arranged in a grid pattern and having a constant width, for separating the plurality of cell regions from each other;

a second trench disposed at an outermost circumference of the plurality of cell regions;

a gate insulating film for covering inner walls of the first trenches and an inner wall of the second trench;

a gate electrode that fills the first trenches and the second trench covered by the gate insulating film;

a cell circumferential region disposed to surround an outer side of the second trench;

an interlayer insulating film disposed on the plurality of cell regions, the first trenches, and the second trench;

a gate contact hole disposed in the interlayer insulating film at an intersection of the first trenches arranged in the grid pattern, the gate contact hole not being provided on the second trench; and

a gate wiring connected to the gate electrode via the gate contact hole.

3. A semiconductor device according to claim 1, wherein each of the plurality of cell regions has rounded corners.

4. A semiconductor device according to claim 1, wherein the gate contact hole is formed on the gate electrode so as to pass through the interlayer insulating film.

2. A semiconductor device, comprising:

a semiconductor substrate;

a body layer disposed in the semiconductor substrate;

a plurality of cell regions, each comprising a source region arranged around a surface layer part of the body layer;

first trenches arranged in a zigzag grid pattern and having a constant width, for separating the plurality of cell regions from each other;

a second trench disposed at an outermost circumference of the plurality of cell regions;

a gate insulating film for covering inner walls of the first trenches and an inner wall of the second trench;

a gate electrode that fills the first trenches and the second trench covered by the gate insulating film;

a cell circumferential region disposed to surround an outer side of the second trench;

an interlayer insulating film disposed on the plurality of cell regions, the first trenches, and the second trench;

a gate contact hole disposed in the interlayer insulating film at an intersection of the first trenches arranged in the zigzag grid pattern, the gate contact hole not being provided on the second trench; and

a gate wiring connected to the gate electrode via the gate contact hole.

5. A semiconductor device according to claim 2, wherein each of the plurality of cell regions has rounded corners.

6. A semiconductor device according to claim 2, wherein the gate contact hole is formed on the gate electrode so as to pass through the interlayer insulating film.

7. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of cell regions formed on the semiconductor substrate;

first trenches arranged in a grid pattern so as to separate the plurality of cell regions from each other;

a second trench disposed at an outermost circumference of the plurality of cell regions;

a gate insulating film covering inner walls of the first trenches and an inner wall of the second trench;

a gate electrode filled the first trenches and the second trench covered by the gate insulating film;

an interlayer insulating film disposed on the plurality of cell regions, the first trenches, and the second trench;

a gate contact hole disposed in the interlayer insulating film at an intersection of the first trenches arranged in the grid pattern, the gate contact hole not being provided on the second trench; and

a gate wiring connected to the gate electrode via the gate contact hole.

8. A semiconductor device according to claim 7, wherein the grid pattern comprises a zigzag grid pattern.

9. A semiconductor device according to claim 8, wherein each of the plurality of cell regions has rounded corners.

10. A semiconductor device according to claim 8, wherein the gate contact hole is formed on the gate electrode so as to pass through the interlayer insulating film.

11. A semiconductor device according to claim 7, wherein each of the plurality of cell regions has rounded corners.

12. A semiconductor device according to claim 7, wherein the gate contact hole is formed on the gate electrode so as to pass through the interlayer insulating film.