Semiconductor device and method of fabricating the same

• US 9,306,070 B2
• Filed: 08/22/2014
• Issued: 04/05/2016
• Est. Priority Date: 11/18/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Baek, Kang-Hyun, Park, Sung-Hyun, Baek, Sang-Hoon, Song, Tae-Joong
• Primary Examiner(s): Mandala, Michelle
• Assistant Examiner(s): DRYE, TYLER B
• Application Number:
  US14/465,968
• Publication Number:
  US 20150137262A1
• Time in Patent Office: 592 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66818 the channel being thinned after patterning, e.g. sacrificial oxidation on fin
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element

Abstract

A semiconductor device includes: active fins protruding from an active layer and extending in a first direction; a gate structure on the active fins extending in a second direction intersecting the first direction; and a spacer on at least one side of the gate structure, wherein each of the active fins includes a first region and a second region adjacent to the first direction in the first direction, and a width of the first region in the second direction is different from a width of the second region in the second direction.

Claims

1. A semiconductor device comprising:

active fins protruding from an active layer and extending in a first direction;

a gate structure on the active fins extending in a second direction intersecting the first direction; and

a spacer on at least one side of the gate structure,

wherein each of the active fins comprises a first region and a second region adjacent to the first region in the first direction, and a width of the first region in the second direction is different from a width of the second region in the second direction; and

wherein the first region is asymmetrical with respect to a centerline in the first direction of each of the active fins.

2. The semiconductor device of claim 1, wherein the first region is under the gate structure, and the second region is under the spacer.

3. The semiconductor device of claim 2, wherein part of the first region is under the spacer.

4. The semiconductor device of claim 2, wherein the width of the first region in the second direction is smaller than the width of the second region in the second direction.

5. The semiconductor device of claim 2, wherein the active fins comprise first through third active fins which are arranged sequentially in the second direction to be separated from each other, wherein a first gap between the first region of the first active fin and the first region of the second active fin is different from a second gap between the first region of the second active fin and the first region of the third active fin.

6. The semiconductor device of claim 2, wherein the active fins comprise first through third active fins which are arranged sequentially in the second direction to be separated from each other, wherein a first gap between the first region of the first active fin and the first region of the second active fin is equal to a second gap between the first region of the second active fin and the first region of the third active fin.

7. The semiconductor device of claim 1, wherein the active fins comprise a first active fin and a second active fin which are separated from each other in the first direction, wherein the first active fin is in the first region, and the second active fin is in the second region.

8. The semiconductor device of claim 7, further comprising a self-aligned contact which electrically connects the first active fin and the second active fin.

9. The semiconductor device of claim 7, wherein a width of the first active fin in the second direction is greater than a width of the second active fin in the second direction, and the first active fin comprises third through fifth active fins which are arranged sequentially in the second direction to be separated from each other, wherein a gap between the third active fin and the fourth active fin is equal to a gap between the fourth active fin and the fifth active fin.

10. The semiconductor device of claim 7, wherein a width of the first active fin in the second direction is greater than a width of the second active fin in the second direction, and the first active fin comprises third through fifth active fins which are arranged sequentially in the second direction to be separated from each other, wherein a gap between the third active fin and the fourth active fin is different from a gap between the fourth active fin and the fifth active fin.

11. The semiconductor device of claim 10, wherein a side of the first active fin is aligned with a side of the second active fin in the first direction.

12. A semiconductor device comprising:

a first transistor; and

a second transistor spaced apart from the first transistor in a first direction,

wherein the first transistor comprises a first active fin which extends in the first direction, and the second transistor comprises a second active fin which is aligned with the first active fin in the first direction, wherein a width of the first active fin in a second direction intersecting the first direction is different from a width of the second active fin in the second direction; and

wherein the first active fin is asymmetrical with respect to a centerline in the first direction through the second active fin.

13. The semiconductor device of claim 12, comprising a static random access memory (SRAM), wherein the first transistor comprises a pull-up transistor, and the second transistor comprises a pull-down transistor.

14. The semiconductor device of claim 12, wherein the width of the first active fin in the second direction is greater than the width of the second active fin in the second direction, and the first active fin comprises third through fifth active fins which are arranged sequentially in the second direction to be separated from each other, wherein a gap between the third active fin and the fourth active fin is equal to a gap between the fourth active fin and the fifth active fin.

15. The semiconductor device of claim 12, wherein a side of the first active fin is aligned with a side of the second active fin in the first direction.

16. A semiconductor device comprising:

a plurality of active fins extending in a first direction;

a gate structure extending in a second direction on a portion of each of the plurality of active fins; and

a spacer on at least one side of the gate structure,

wherein each of the plurality of active fins comprises a first region and a second region,

wherein the first region of each of the plurality of active fins comprises a first width in the second direction and the second region of each of the plurality of active fins comprises a second width in the second direction,

wherein the first width is smaller than the second width, and

wherein the first region is asymmetrical with respect to a centerline in the first direction of each of the active fins.

17. The semiconductor device of claim 16, wherein part of the first region is under the gate structure and part of the first region is under the spacer, and the second region is under the spacer.

18. The semiconductor device of claim 16, wherein the plurality of active fins comprise first through third active fins which are arranged sequentially in the second direction to be separated from each other, wherein a first gap between the first region of the first active fin and the first region of the second active fin is different from a second gap between the first region of the second active fin and the first region of the third active fin.

19. The semiconductor device of claim 16, wherein the plurality of active fins comprise first through third active fins which are arranged sequentially in the second direction to be separated from each other, wherein a first gap between the first region of the first active fin and the first region of the second active fin is equal to a second gap between the first region of the second active fin and the first region of the third active fin.