Semiconductor device and method for manufacturing the same

• US 9,306,079 B2
• Filed: 10/15/2013
• Issued: 04/05/2016
• Est. Priority Date: 10/17/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Suzawa, Hideomi
• Primary Examiner(s): Ingham, John C
• Application Number:
  US14/054,110
• Publication Number:
  US 20140103339A1
• Time in Patent Office: 903 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/467 using masks
• CPC Class Codes: H01L 21/477 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/38 - H01L21/449 and H01L21/461 - H01L21/475 take precedence
• CPC Class Codes: H01L 29/247 Amorphous materials
• CPC Class Codes: H01L 29/263 Amorphous materials
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device formed using an oxide semiconductor layer and having small electrical characteristic variation is provided. A highly reliable semiconductor device including an oxide semiconductor layer and exhibiting stable electric characteristics is provided. Further, a method for manufacturing the semiconductor device is provided. In the semiconductor device, an oxide semiconductor layer is used for a channel formation region, a multilayer film which includes an oxide layer in which the oxide semiconductor layer is wrapped is provided, and an edge of the multilayer film has a curvature in a cross section.

Claims

1. A semiconductor device comprising:

a multilayer film comprising an oxide semiconductor layer and an oxide layer;

a source electrode and a drain electrode in contact with the oxide layer; and

a gate electrode overlapping with the oxide semiconductor layer with a gate insulating film therebetween,

wherein a thickness of the multilayer film is greater than or equal to 1/50 and less than or equal to 50 times as large as a curvature radius of a side surface of the multilayer film,

wherein the oxide semiconductor layer and the oxide layer contain at least indium,

wherein the oxide semiconductor layer is wrapped by the oxide layer, and

wherein an edge of the multilayer film in a cross section has a curvature.

2. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer has a higher proportion of indium than the oxide layer.

3. The semiconductor device according to claim 1,

wherein the oxide layer and the oxide semiconductor layer contain indium, zinc, and an element M,

wherein the element M is one of aluminum, titanium, silicon, gallium, germanium, yttrium, zirconium, tin, lanthanum, cerium, and hafnium, and

wherein the oxide layer has a higher proportion of the element M than the oxide semiconductor layer.

4. The semiconductor device according to claim 1,

wherein the oxide layer has a larger energy gap than the oxide semiconductor layer.

5. The semiconductor device according to claim 1,

wherein a gap between an energy at the bottom of a conduction band of the oxide layer and an energy at the bottom of a conduction band of the oxide semiconductor layer is greater than or equal to 0.05 eV and less than or equal to 2 eV.

6. The semiconductor device according to claim 1, further comprising a base insulating film below the multilayer film,

wherein a region of the base insulating film overlapping with the multilayer film has a larger thickness than the other region of the base insulating film.

7. The semiconductor device according to claim 6,

wherein the base insulating film includes a first region overlapping with the multilayer film, a second region surrounding the first region, and a third region surrounding the second region,

wherein the second region has a smaller thickness than the first region, and

wherein the third region has a smaller thickness than the second region.

8. A semiconductor device comprising:

a first oxide layer;

an oxide semiconductor layer over the first oxide layer;

a second oxide layer over the oxide semiconductor layer;

a third oxide layer on a side surface of the oxide semiconductor layer;

a source electrode and a drain electrode in contact with the second oxide layer and the third oxide layer; and

a gate electrode overlapping with the oxide semiconductor layer with a gate insulating film therebetween,

wherein a thickness of the third oxide layer is larger than a thickness of the second oxide layer,

wherein the oxide semiconductor layer, the first oxide layer, the second oxide layer and the third oxide layer contain at least indium, and

wherein a side surface of the third oxide layer in a cross section has a curvature.

9. The semiconductor device according to claim 8,

wherein a gap between an energy at the bottom of a conduction band of each of the first oxide layer, the second oxide layer and the third oxide layer and an energy at the bottom of a conduction band of the oxide semiconductor layer is greater than or equal to 0.05 eV and less than or equal to 2 eV.

10. The semiconductor device according to claim 8, wherein a total thickness of the first oxide layer, the oxide semiconductor layer and the second oxide layer is greater than or equal to 1/50 and less than or equal to 50 times as large as a curvature radius of the side surface of the third oxide layer.

11. The semiconductor device according to claim 8, further comprising a base insulating film below the first oxide layer,

wherein a region of the base insulating film overlapping with the first oxide layer, the second oxide layer and the third oxide layer has a larger thickness than the other region of the base insulating film.

12. The semiconductor device according to claim 11,

wherein the base insulating film includes a first region overlapping with the first oxide layer, the second oxide layer and the third oxide layer, a second region surrounding the first region, and a third region surrounding the second region,

wherein the second region has a smaller thickness than the first region, and

wherein the third region has a smaller thickness than the second region.