High efficiency light emitting diode

• US 9,306,120 B2
• Filed: 11/20/2013
• Issued: 04/05/2016
• Est. Priority Date: 11/21/2012
• Status: Active Grant

• Current Assignee: Seoul Viosys Co., Ltd. (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Seoul Viosys Co., Ltd. (Seoul Semiconductor Co., Ltd.)
• Inventors: Kim, Da Hye, You, Jong Kyun, Kim, Chang Yeon, Im, Tae Hyuk
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): Jang, Bo Bin
• Application Number:
  US14/085,092
• Publication Number:
  US 20140138729A1
• Time in Patent Office: 867 Days
• Field of Search: 257/78, 257/79, 257 95- 99, 257/103, 257/680, 257/E33.005, 257/E33.023, 257/E33.064, 257/E33.067, 438/27, 438/46
• US Class Current: 1/1
• CPC Class Codes: H01L 2933/0025 relating to coatings
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating

Abstract

A method of fabricating method light-emitting diode according to an exemplary embodiment of the present invention includes forming a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer on a first substrate, forming a second substrate on the second conductivity-type semiconductor layer, separating the first substrate from the first conductivity-type semiconductor layer, forming a mask pattern including a plurality of openings on the first conductivity-type semiconductor layer exposed after separating the substrate, etching the first conductivity-type semiconductor layer having the mask pattern disposed thereon to form a plurality of recesses separated from each other, removing the mask pattern, and etching a surface of the first conductivity-type semiconductor layer to form a sub-micro texture.

Claims

1. A light-emitting diode, comprising:

a second conductivity-type semiconductor layer disposed on a support substrate;

a first conductivity-type semiconductor layer disposed on the second conductivity-type semiconductor layer;

an active layer disposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer;

a passivation layer disposed on the first conductivity-type semiconductor layer, the second conductivity-type semiconductor, and the active layer;

an insulating pattern layer disposed on a first region of the support substrate; and

an electrode pad disposed on the first conductivity-type semiconductor layer,

wherein;

the first conductivity-type semiconductor layer comprises a plurality of recesses spaced apart from each other and a sub-micro texture disposed on an uppermost surface of the first conductivity-type semiconductor layer opposite to the support substrate excluding the plurality of recesses;

the passivation layer is disposed in the plurality of recesses and on the sub-micro texture of the first conductivity-type semiconductor layer;

the electrode pad is disposed on a portion of the sub-micro texture and at least one of the plurality of recesses of the first conductivity-type semiconductor layer.

2. The light-emitting diode of claim 1, wherein the sub-micro texture comprises sub-micro cones.

3. The light-emitting diode of claim 2, wherein the passivation layer comprises at least one conical portion disposed on the sub-micro cones, the at least one conical portion comprising a gentler slope than the sub-micro cones.

4. The light-emitting diode of claim 2, wherein the plurality of recesses comprise micro-conical recesses each comprising a circular or hexagonal inlet.

5. The light-emitting diode of claim 4, wherein each micro conical recess comprises a gentler side slope than a side slope of the sub-micro cones.

6. The light-emitting diode of claim 5, wherein the micro conical recesses comprise a U-shape cross-section and the sub-micro cones comprise an inverted V-shape cross-section.

7. The light-emitting diode of claim 2, wherein the sub-micro cones comprise an average height of 0.5 μ

m or less.

8. The light-emitting diode of claim 1, wherein the at least one of the plurality of recesses and the uppermost surface of the first conductivity-type semiconductor layer form a concavo-convex shape.

9. The light-emitting diode of claim 1, further comprising a metal layer disposed between the second conductivity-type semiconductor layer and the support substrate.

10. The light-emitting diode of claim 9, wherein the metal layer comprises a reflective metal layer and a barrier metal layer,

wherein the reflective metal layer is disposed on a second region of the support substrate, the barrier metal layer is disposed between the reflective metal layer and the insulating pattern layer and the support substrate, and the reflective metal layer and the insulating pattern layer are disposed on the barrier metal layer.

11. The light-emitting diode of claim 9, further comprising a bonding layer disposed between the support substrate and the metal layer.

12. The light-emitting diode of claim 1,

wherein the electrode pad is disposed on a first region arranged above the insulating pattern layer.

13. The light-emitting diode of claim 12, further comprising an electrode extension extending from the electrode pad.

14. The light-emitting diode of claim 13, wherein the electrode extension is disposed on a second region arranged above the insulating pattern layer, the second region being spaced apart from the first region.

15. The light-emitting diode of claim 14, wherein the electrode extension is disposed on a peripheral side surface of the first conductivity-type semiconductor layer.

16. A light-emitting diode, comprising:

a second conductivity-type semiconductor layer disposed on a support substrate;

a first conductivity-type semiconductor layer disposed on the second conductivity-type semiconductor layer;

an active layer disposed between the first conductivity-type semiconductor layer and the second conductivity-type semiconductor layer;

a passivation layer disposed on the first conductivity-type semiconductor layer, the second conductivity-type semiconductor, and the active layer;

an insulating pattern layer disposed on a first region of the support substrate;

an electrode pad disposed on the first conductivity-type semiconductor layer; and

an electrode extension extending from the electrode pad,

wherein;

the first conductivity-type semiconductor layer comprises a plurality of recesses spaced apart from each other and a sub-micro texture disposed on an uppermost surface of the first conductivity-type semiconductor layer opposite to the support substrate excluding the plurality of recesses;

the passivation layer disposed on the first conductivity-type semiconductor layer is disposed in the plurality of recesses and on the sub-micro texture of the first conductivity-type semiconductor layer;

the electrode pad is disposed on a portion of the sub-micro texture and at least one of the plurality of recesses of the first conductivity-type semiconductor layer;

the electrode pad is disposed on a first region of the first conductivity-type semiconductor layer arranged over the insulating pattern layer; and

the electrode extension is disposed on a second region of the first conductivity-type semiconductor layer arranged over the insulating pattern layer, the second region of the first conductivity-type semiconductor layer being spaced apart from the first region of the first conductivity-type semiconductor layer.