Receiver having a wide common mode input range

• US 9,306,509 B2
• Filed: 07/27/2012
• Issued: 04/05/2016
• Est. Priority Date: 07/27/2012
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lim, Siok Wei, Hsieh, Cheng-Hsiang, Savoj, Jafar
• Primary Examiner(s): Jackson, Stephen W
• Application Number:
  US13/560,944
• Publication Number:
  US 20140029143A1
• Time in Patent Office: 1,348 Days
• Field of Search: 361/56
• US Class Current: 1/1
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/444 Diode used as protection means in an amplifier, e.g. as a limiter or as a switch
• CPC Class Codes: H03F 2200/498 A resistor being added in the source circuit of a transistor amplifier stage as degenerating element
• CPC Class Codes: H03F 2203/45091 Two complementary type differential amplifiers are paralleled, e.g. one of the p-type and one of the n-type
• CPC Class Codes: H03F 2203/45092 Two current sources bias one set of two common base transistors cascaded with two other common base transistors, the common base transistors being driven complementary
• CPC Class Codes: H03F 2203/45466 the CSC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
• CPC Class Codes: H03F 2203/45494 the CSC comprising one or more potentiometers
• CPC Class Codes: H03F 2203/45568 the IC comprising one or more diodes as shunt to the input leads
• CPC Class Codes: H03F 3/45224 Complementary Pl types having parallel inputs and being supplied in parallel
• CPC Class Codes: H03F 3/45233 Folded cascode stages
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
• CPC Class Codes: H03H 11/1213 using transistor amplifiers H03H11/1204 takes precedence; parallel-T filters H03H11/1295
• CPC Class Codes: H04L 25/0276 Arrangements for coupling common mode signals
• CPC Class Codes: H04L 27/0002 analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line duplex arrangements H04L5/143

Abstract

In one embodiment, a differential amplifier is provided. Gates of a first differential pair of transistors, of a first conductivity type, and a second pair or transistors, of a second conductivity type are coupled to first and second input terminals of the differential amplifier. A first pair of adjustable current sources are configured to adjust respective tail currents of the first differential pair of transistors in response to a first bias current control signal. A second pair of adjustable current sources are configured to adjust respective tail currents of the second differential pair of transistors in response to the first bias current control signal. A third pair of adjustable current sources are configured to adjust respective currents through the second differential pair of transistors in response to a second bias current control signal.

Claims

1. A differential amplifier, comprising:

first and second input terminals;

a first differential pair of transistors having a first conductivity type and gates coupled to the first and second input terminals, respectively;

a second differential pair of transistors having a second conductivity type and gates coupled to the first and second input terminals, respectively;

a first pair of adjustable current sources coupled to the first differential pair of transistors and configured to adjust respective tail currents of the first differential pair of transistors in response to a first bias current control signal;

a second pair of adjustable current sources coupled to the second differential pair of transistors and configured to adjust respective tail currents of the second differential pair of transistors in response to the first bias current control signal; and

a third pair of adjustable current sources coupled to the second differential pair of transistors and configured to adjust respective currents through the second differential pair of transistors in response to a second bias current control signal.

2. The differential amplifier of claim 1, further comprising a constant transconductance bias generator coupled to the first and second pairs of adjustable current sources and configured to generate the first bias current control signal.

3. The differential amplifier of claim 1, further comprising, a bias generation circuit coupled to the third pair of adjustable current sources and configured to generate the second bias current control signal from the first bias current control signal.

4. The differential amplifier of claim 1, wherein:

a first transistor of the first differential pair of transistors has a drain and a source, the drain coupled to receive a current from a first current source and coupled to a first output terminal of the differential amplifier, and the source coupled to a first one of the first pair of adjustable current sources;

a second transistor of the first differential pair of transistors has a drain and a source, the drain coupled to receive current from a second current source and coupled to a second output terminal of the differential amplifier, and the source coupled to a second one of the first pair of adjustable current sources;

a first transistor of the second differential pair of transistors has a source coupled to a first one of the third pair of adjustable current sources and has a drain coupled to a first one of the second pair of adjustable current sources; and

a second transistor of the second differential pair of transistors has a source coupled to a second one of the third pair of adjustable current sources and has a drain coupled to a second one of the second pair of adjustable current sources.

5. The differential amplifier of claim 4, further comprising:

a first MOSFET coupled between the drain of the first transistor of the second differential pair of transistors and the first output terminal of the differential amplifier, the first MOSFET having a gate coupled to receive a third bias current control signal; and

a second MOSFET coupled between the drain of the second transistor of the second differential pair of transistors and the second output terminal of the differential amplifier, the second MOSFET having a gate coupled to receive a third bias current control signal.

6. The differential amplifier of claim 4, further comprising a control circuit configured to:

while operating in a first mode, enable operation of the first differential pair of transistors and disable operation of the second differential pair of transistors; and

while operating in a second mode, enable operation of the second differential pair of transistors and disable operation of the first differential pair of transistors.

7. The differential amplifier of claim 6, wherein the control circuit is configured to:

perform the disabling of operation of the first differential pair of transistors by disconnecting the first bias current control signal from the first pair of adjustable current sources; and

perform the disabling of operation of the second differential pair of transistors by disconnecting the first bias current control signal from the third pair of adjustable current sources, disconnecting the second bias current control signal from the second pair of adjustable current sources, and disconnecting the third bias current control signal from the gates of the first and second MOSFETs.

8. The differential amplifier of claim 4, further comprising:

a first programmable resistor coupled between the sources of the first differential pair of transistors; and

a second programmable resistor coupled between the sources of the second differential pair of transistors, the first and second programmable resistors configured to adjust gain and frequency response of the differential amplifier in response to a gain control signal.

9. The differential amplifier of claim 4, further comprising:

a zero frequency adjustment circuit coupled to the first and second differential pairs of transistors, the zero frequency adjustment circuit configured to adjust a zero frequency of the differential amplifier in response to a frequency control signal.

10. The differential amplifier of claim 9, wherein the zero frequency adjustment circuit includes first, second, third, and fourth, programmable capacitors coupled between respective sources of the first and second differential pairs of transistors and a ground voltage.

11. The differential amplifier of claim 1, further comprising a termination resistor circuit coupled between the first and second input terminals.

12. The differential amplifier of claim 1, further comprising an electrostatic discharge circuit coupled to the first and second input terminals.

13. An analog front-end circuit, comprising:

a first electrostatic discharge circuit having inputs for receiving a differential signal from a transmission medium;

termination resistors coupled to differential outputs of the first electrostatic discharge circuit and configured to match the impedance of the analog front end to impedance of the transmission medium;

an equalizer circuit including a first differential amplifier circuit coupled to receive the differential signal from differential outputs of the termination resistors, the first differential amplifier circuit including;

an NMOS differential pair having inputs connected to the differential outputs of the termination resistors, the NMOS differential pair and configured to receive and amplify the differential signal using a high common mode voltage, the NMOS differential pair biased during operation by a first pair of adjustable current sources in response to a first bias current control signal;

a PMOS differential pair having inputs connected to the differential outputs of the termination resistors, the PMOS differential pair configured to receive and amplify the differential signal using a low common mode voltage, the PMOS differential pair biased during operation by a second pair of adjustable current sources in response to the first bias current control signal and by a third pair of adjustable current sources in response to a second bias current control signal; and

a control circuit configured to;

when operating in a low common mode, enable operation of the PMOS differential pair and disable operation of the NMOS differential pair; and

when operating in a high common mode, enable operation of the NMOS differential pair and disable operation of the PMOS differential pair.

14. The analog front-end circuit of claim 13, wherein the equalizer circuit further includes:

a second differential amplifier circuit coupled to receive the differential signal from differential outputs of the first differential amplifier circuit; and

a third differential amplifier circuit coupled to receive the differential signal from differential outputs of the second differential amplifier circuit.

15. The analog front-end circuit of claim 14, wherein:

the first differential amplifier circuit is configured to perform high frequency boost of the differential signal;

the second differential amplifier circuit is configured to perform long-tail cancellation of the differential signal; and

the third differential amplifier circuit is configured to boost gain of the differential signal.

16. The analog front-end circuit of claim 14, further comprising:

a constant transconductance bias generator connected to the first and second pairs of adjustable current sources, the transconductance bias generator configured to generate the first bias current control signal.

17. The analog front-end circuit of claim 14, further comprising a biasing circuit connected to the third pair of adjustable current sources and configured to generate the second bias current control signal from the first bias voltage.

18. A method of amplifying a differential signal, comprising:

providing the differential signal to inputs of a PMOS differential pair;

providing the differential signal to inputs of an NMOS differential pair;

in response to a common mode control signal indicating a high common mode;

enabling the NMOS differential pair by biasing the NMOS differential pair with a first pair of adjustable current sources in response to a first bias current control signal; and

disabling the PMOS differential pair; and

in response to the common mode control signal indicating a low common mode;

enabling the PMOS differential pair by biasing the PMOS differential pair with a second pair of adjustable current sources in response to the first bias current control signal and biasing the PMOS differential pair with a third pair of adjustable current sources in response to a second bias current control signal; and

disabling the NMOS differential pair.

19. The method of claim 18, wherein:

disabling the NMOS differential pair includes removing the first bias current control signal from the first pair adjustable current sources; and

disabling the PMOS differential pair includes;

removing the first bias current control signal from the second pair of adjustable current sources; and

removing the second bias current control signal from the third pair of adjustable current sources.

20. The method of claim 19, further comprising:

in response to the common mode control signal indicating the low common mode, respectively coupling first and second outputs of the PMOS differential amplifier to first and second outputs of the NMOS differential amplifier with a pair of transistors by applying a third bias current control signal to the pair of transistors; and

in response to the common mode control signal indicating the low common mode, disconnecting the first and second outputs of the PMOS differential amplifier from the first and second outputs of the NMOS differential amplifier with a pair of transistors by removing the third bias current control signal from the pair of transistors.