Apparatus, system, and method for reconfiguring an array of storage elements

• US 9,306,599 B2
• Filed: 05/23/2014
• Issued: 04/05/2016
• Est. Priority Date: 05/18/2009
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Intelligent Intellectual Property Holdings LLC
• Inventors: Flynn, David, Thatcher, Jonathan, Aune, Joshua, Fillingim, Jeremy, Inskeep, Bill, Strasser, John, Vigor, Kevin
• Primary Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US14/286,712
• Publication Number:
  US 20140258775A1
• Time in Patent Office: 683 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0766 Error or fault reporting or storing
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 11/1092 Rebuilding, e.g. when physically replacing a failing disk
• CPC Class Codes: G06F 11/1096 Parity calculation or recalculation after configuration or reconfiguration of the system
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Abstract

Apparatuses, systems, and methods are disclosed for reconfiguring an array of storage elements. A storage element error module is configured to determine that one or more storage elements in an array of storage elements are in error. An array of storage elements stores a first ECC block and first parity data generated from the first ECC block. A data reconfiguration module is configured to generate a second ECC block comprising at least a portion of data of a first ECC block. A new configuration storage module is configured to store a second ECC block and associated second parity data on fewer storage elements than a number of storage elements in an array.

Claims

1. An apparatus, comprising:

a flash memory device comprising an array of storage elements; and

a storage controller configured to;

write a first data stripe across a first plurality of the storage elements, the first data stripe comprising a first set of Error Correcting Code (ECC) data chunks and first parity information associated with the first set of ECC data chunks, the first parity information being written to a first parity storage element of the first plurality of storage elements; and

write a second data stripe across a second plurality of the storage elements, the second data stripe comprising a second set of ECC data chunks and second parity information associated with the second set of ECC data chunks, the second parity information being written to a second parity storage element of the second plurality of storage elements;

wherein the position of the first parity storage element relative to the storage elements comprising first ECC data chunks is different to the position of the second parity storage element relative to the storage elements comprising second ECC data chunks.

2. The apparatus of claim 1, wherein

the first plurality of storage elements are comprised within a first row of the array of storage elements;

and

the second plurality of storage elements are comprised within a second row of the array of storage elements.

3. The apparatus of claim 1, further comprising:

a storage element error module configured to determine, based on an ECC, that reading data from one or more of the first plurality of solid-state storage elements produces erroneous data; and

a data regeneration module configured to regenerate the data from the first parity information;

wherein the storage element error module and the data regeneration module comprise one or more of logic hardware and a non-transitory computer readable medium having executable code stored thereon.

4. The apparatus of claim 1, wherein the storage controller is configured to:

write the first parity information to a plurality of first parity storage elements; and

write the second parity information to a plurality of second parity storage elements.

5. A method comprising a storage controller:

writing a first data stripe across a first plurality of storage elements of a flash memory, the first data stripe comprising a first set of Error Correction Code (ECC) data chunks and first parity information associated with the first set of ECC data chunks, the first parity information being written to a first parity storage element; and

writing a second data stripe across a second plurality of the storage elements, the second data stripe comprising a second set of ECC data chunks and second parity information associated with the second set of ECC data chunks, the second parity information being written to a second parity storage element;

wherein the position of the first parity storage element relative to the storage elements comprising first ECC data chunks is different to the position of the second parity storage element relative to the storage elements comprising second ECC data chunks.

6. The method of claim 5, wherein

the first plurality of storage elements are comprised within a first row of the array of storage elements;

and

the second plurality of storage elements are comprised within a second row of the array of storage elements.

7. The method of claim 5, further comprising the storage controller:

writing the first parity information to a plurality of first parity storage elements; and

writing the second parity information to a plurality of second parity storage elements.

8. A non-transitory computer-readable medium comprising instructions which, when executed, cause a processor to:

write a first data stripe across a first plurality of storage elements of a flash memory, the first data stripe comprising a first set of Error Correction Code (ECC) data chunks and first parity information associated with the first set of ECC data chunks, the first parity information being written to a first parity storage element; and

write a second data stripe across a second plurality of the storage elements, the second data stripe comprising a second set of ECC data chunks and second parity information associated with the second set of ECC data chunks, the second parity information being written to a second parity storage element;

wherein the position of the first parity storage element relative to the storage elements comprising first ECC data chunks is different to the position of the second parity storage element relative to the storage elements comprising second ECC data chunks.

9. The non-transitory computer-readable medium of claim 8, wherein

the first plurality of storage elements are comprised within a first row of the array of storage elements;

and

the second plurality of storage elements are comprised within a second row of the array of storage elements.

10. The non-transitory computer-readable medium of claim 8, wherein, when executed, the instructions further cause a processor to:

write the first parity information to a plurality of first parity storage elements; and

write the second parity information to a plurality of second parity storage elements.

11. An apparatus, comprising:

a flash memory device comprising N banks of storage elements, where N>

1; and

a storage controller configured to;

write a first data stripe across a first plurality of the storage elements, wherein each of the first plurality of storage elements is comprised within a respective one of the N banks of storage elements, the first data stripe comprising a first set of error correcting code (ECC) data chunks and first parity information associated with the first set of ECC data chunks, the first parity information being written to a storage element comprised within a first bank of storage elements; and

write a second data stripe across a second plurality of the storage elements, wherein each of the second plurality of storage elements is comprised within a respective one of the N banks of storage elements, the second data stripe comprising a second set of ECC data chunks and second parity information associated with the second set of ECC data chunks, the second parity information being written to a storage element comprised within a second bank of storage elements, wherein the second bank of storage elements is different to the first bank of storage elements.