Fractional-N PLL-based CDR with a low-frequency reference
First Claim
1. An apparatus for clock and data recovery, comprising:
- a fractional-N phase-locked loop for receiving a reference signal, and for providing a proportional signal and an integral signal;
a ring oscillator of the fractional-N phase-locked loop for receiving the proportional signal and the integral signal, and for providing an oscillation signal at a clock frequency substantially greater than a reference frequency of the reference signal;
a data-to-frequency control word converter for receiving data input and the oscillation signal, and for providing a frequency control word;
a fractional-N divider of the fractional-N phase-locked loop for receiving the frequency control word and the oscillation signal, and for providing a feedback clock signal to a phase-frequency detector of the fractional-N phase-locked loop; and
the phase-frequency detector of the fractional-N phase-locked loop for receiving the reference signal and the feedback clock signal, and for adjusting a phase and frequency of the oscillation signal.
1 Assignment
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Accused Products
Abstract
An apparatus relates generally to clock and data recovery. A fractional-N phase-locked loop is for receiving a reference signal, and for providing a proportional signal and an integral signal. A ring oscillator of the fractional-N phase-locked loop is for receiving the proportional signal and the integral signal, and for providing an oscillation signal at a clock frequency substantially greater than a reference frequency of the reference signal. A data-to-frequency control word converter is for receiving data input and the oscillation signal, and for providing a frequency control word. A fractional-N divider of the fractional-N phase-locked loop is for receiving the frequency control word and the oscillation signal, and for providing a feedback clock signal to a phase-frequency detector of the fractional-N phase-locked loop. The phase-frequency detector is for receiving the reference signal and the feedback clock signal, and for adjusting a phase and frequency of the oscillation signal.
31 Citations
20 Claims
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1. An apparatus for clock and data recovery, comprising:
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a fractional-N phase-locked loop for receiving a reference signal, and for providing a proportional signal and an integral signal; a ring oscillator of the fractional-N phase-locked loop for receiving the proportional signal and the integral signal, and for providing an oscillation signal at a clock frequency substantially greater than a reference frequency of the reference signal; a data-to-frequency control word converter for receiving data input and the oscillation signal, and for providing a frequency control word; a fractional-N divider of the fractional-N phase-locked loop for receiving the frequency control word and the oscillation signal, and for providing a feedback clock signal to a phase-frequency detector of the fractional-N phase-locked loop; and the phase-frequency detector of the fractional-N phase-locked loop for receiving the reference signal and the feedback clock signal, and for adjusting a phase and frequency of the oscillation signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A serial link system for supporting multiple frequencies via multiple lanes, comprising:
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a reference oscillator for providing a reference signal; a plurality of clock and data recovery blocks corresponding to the multiple lanes; the plurality of clock and data recovery blocks commonly coupled for receiving the reference signal; wherein each of the plurality of clock and data recovery blocks comprises; a fractional-N phase-locked loop having a ring oscillator for providing an oscillation signal at a clock frequency substantially greater than a reference frequency of the reference signal; a data-to-frequency control word converter for receiving a data input for a corresponding lane of the multiple lanes, for receiving the oscillation signal, and for providing a frequency control word as output; and a fractional-N divider of the fractional-N phase-locked loop for receiving the frequency control word and the oscillation signal, and for providing a feedback clock signal to a phase-frequency detector of the fractional-N phase-locked loop. - View Dependent Claims (12, 13, 14, 15, 16)
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17. A method for clock and data recovery, comprising:
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receiving a reference signal by a fractional-N phase-locked loop; generating a proportional signal and an integral signal by the fractional-N phase-locked loop; receiving the proportional signal and the integral signal by a ring oscillator of the fractional-N phase-locked loop; outputting an oscillation signal by the ring oscillator at a clock frequency substantially greater than a reference frequency of the reference signal; receiving a data input and the oscillation signal by a data-to-frequency control word converter; providing a frequency control word by the data-to-frequency control word converter; receiving the frequency control word and the oscillation signal by a fractional-N divider of the fractional-N phase-locked loop; dividing the oscillation signal by the fractional-N divider to output a feedback clock signal; feeding back the feedback clock signal to a phase-frequency detector of the fractional-N phase-locked loop; receiving the reference signal and the feedback clock signal by the phase-frequency detector of the fractional-N phase-locked loop; providing an up signal and a down signal from the phase-frequency detector; and adjusting a phase and frequency of the oscillation signal responsive to the up signal and the down signal. - View Dependent Claims (18, 19, 20)
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Specification