Power-line communications with communication channel to and/or from endpoint circuits with authentication methodology

• US 9,306,736 B1
• Filed: 04/10/2015
• Issued: 04/05/2016
• Est. Priority Date: 09/30/2010
• Status: Active Grant

• Current Assignee: Landis+Gyr Inc. (Landis+Gyr Group AG)
• Original Assignee: Landis+Gyr Inc. (Landis+Gyr Group AG)
• Inventors: Bonicatto, Damian
• Primary Examiner(s): Truong, Thanhnga B
• Assistant Examiner(s): Lane, Gregory
• Application Number:
  US14/683,298
• Time in Patent Office: 361 Days
• Field of Search: 713/162, 713/170
• US Class Current: 1/1
• CPC Class Codes: H04B 2203/5408 using protocols
• CPC Class Codes: H04B 2203/5416 by adding signals to the wave form of the power source
• CPC Class Codes: H04B 2203/5441 Wireless systems or telephone
• CPC Class Codes: H04B 2203/5445 Local network
• CPC Class Codes: H04B 3/54 Systems for transmission via power distribution lines
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: H04L 1/0046 Code rate detection or code type detection H04L1/0038 takes precedence; detection of the data rate H04L25/0262; for packet format H04L1/0091
• CPC Class Codes: H04L 2209/24 Key scheduling, i.e. generating round keys or sub-keys for block encryption
• CPC Class Codes: H04L 2209/34 Encoding or coding, e.g. Huffman coding or error correction
• CPC Class Codes: H04L 2209/80 Wireless network architectures or network communication protocols for wireless network security H04W12/00
• CPC Class Codes: H04L 63/08 for authentication of entities cryptographic mechanisms or cryptographic arrangements for entity authentication H04L9/32
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
• CPC Class Codes: H04L 9/0819 Key transport or distribution, i.e. key establishment techniques where one party creates or otherwise obtains a secret value, and securely transfers it to the other(s) network architectures or network communication protocols for key distribution in a packet data network H04L63/062
• CPC Class Codes: H04L 9/0827 involving distinctive intermediate devices or communication paths network architectures or network communication protocols using different networks H04L63/18
• CPC Class Codes: H04L 9/32 including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials

Abstract

In a power-line communication system, a data processing electronic circuitry can receive a plurality of symbols from a plurality of endpoint circuits and over a plurality of communications channels on power lines in a power-line communication system. A first symbol of the plurality of symbols can be decrypted using a first decryption key that is assigned to a first endpoint circuit. From the first decryption, a first measure of error is computed that includes a first bit error rate. The first symbol is decrypted using a second decryption key that is assigned to a second endpoint circuit. From the second decryption, a second measure of error is computed that includes a second bit error rate. The first and second bit error rates are compared to a threshold error measure to determine validity.

Claims

1. For use in a power-line communication system, a method performed by data processing electronic circuitry, the method comprising:

receiving a plurality of symbols from a plurality of endpoint circuits and over a plurality of communications channels on power lines in the power-line communication system;

obtaining respective and different decryption keys from an encryption table that lists the respective and different decryption keys and corresponding assignments to the plurality of endpoint circuits;

decrypting a first symbol of the plurality of symbols using a first decryption key that is assigned to a first endpoint circuit;

computing, from the first symbol as decrypted using the first decryption key, a first measure of error that includes a first bit error rate;

decrypting the first symbol using a second decryption key that is assigned to a second endpoint circuit;

computing, from the first symbol as decrypted using the second decryption key, a second measure of error that includes a second bit error rate;

comparing the first and second bit error rates to a threshold error measure;

identifying, in response to the first bit error rate exceeding the threshold error measure, the first symbol as a valid symbol from the first endpoint circuit; and

logging the first symbol as valid relative to the first endpoint circuit.

2. The method of claim 1, further comprising:

decrypting, for each of the plurality of symbols, using respective and different decryption keys for each of the plurality of endpoint circuits.

3. The method of claim 2, further comprising:

computing, for each of the plurality of symbols and each of the different decryption keys, bit error rates; and

logging, in response to the bit error rates, at least some of the plurality of symbols relative to a corresponding endpoint circuit of the plurality of endpoint circuits.

4. The method of claim 2, wherein the decryption keys for each of the plurality of endpoint circuits are symmetric encryption keys.

5. The method of claim 2, further comprising:

discarding at least one symbol of the plurality of symbols in response to a bit error rate for the at least one symbol being below the threshold error measure.

6. The method of claim 1, wherein computing, from the first symbol as decrypted using the first decryption key, the first measure of error includes using forward error correction data that is present in the first symbol.

14. The method of claim 1, further including identifying, in response to the first bit error rate not exceeding the threshold error measure, the first symbol as being from a different endpoint circuit of the plurality of endpoint circuits.

15. The method of claim 1, further including:

identifying the first endpoint circuit based on the decryption key used to recover data from the signal; and

logging the first symbol as a valid symbol for the first endpoint circuit and based on the identity of the first endpoint circuit.

7. For use in a power-line communication system, a non-transitory computer readable storage medium encoded with computer instructions that, when executed by a computer, cause the computer to perform operations comprising:

receiving a plurality of symbols from a plurality of endpoint circuits and over a plurality of communications channels on power lines in the power-line communication system;

obtaining respective and different decryption keys from an encryption table that lists the respective and different decryption keys and corresponding assignments to the plurality of endpoint circuits;

decrypting a first symbol of the plurality of symbols using a first decryption key that is assigned to a first endpoint circuit;

computing, from the first symbol as decrypted using the first decryption key, a first measure of error that includes a first bit error rate;

decrypting the first symbol using a second decryption key that is assigned to a second endpoint circuit;

computing, from the first symbol as decrypted using the second decryption key, a second measure of error that includes a second bit error rate;

comparing the first and second bit error rates to a threshold error measure;

identifying, in response to the first bit error rate exceeding the threshold error measure, the first symbol as a valid symbol from the first endpoint circuit; and

logging the first symbol as valid relative to the first endpoint circuit.

8. A power-line communication system comprising:

a power-distribution processing unit, including a circuit, configured to couple to a set of endpoints via power lines, the processing unit including one or more processors configured to interact with the set of endpoints and further configured to;

receive a plurality of symbols from a plurality of endpoint circuits and over a plurality of communications channels on power lines in the power-line communication system;

obtain respective and different decryption keys from an encryption table that lists the respective and different decryption keys and corresponding assignments to the plurality of endpoint circuits;

decrypt a first symbol of the plurality of symbols using a first decryption key that is assigned to a first endpoint circuit;

compute, from the first symbol as decrypted using the first decryption key, a first measure of error that includes a first bit error rate;

decrypt the first symbol using a second decryption key that is assigned to a second endpoint circuit;

compute, from the first symbol as decrypted using the second decryption key, a second measure of error that includes a second bit error rate;

compare the first and second bit error rates to a threshold error measure;

identify, in response to the first bit error rate exceeding the threshold error measure, the first symbol as a valid symbol from the first endpoint circuit; and

log the first symbol as valid relative to the first endpoint circuit.

9. The system of claim 8, wherein the power-distribution processing unit is further configured to:

decrypt, for each of the plurality of symbols, using respective and different decryption keys for each of the plurality of endpoint circuits.

10. The system of claim 9, wherein the power-distribution processing unit is further configured to:

compute, for each of the plurality of symbols and each of the different decryption keys, bit error rates; and

log, in response to the bit error rates, at least some of the plurality of symbols relative to a corresponding endpoint circuit of the plurality of endpoint circuits.

11. The system of claim 9, wherein the decryption keys for each of the plurality of endpoint circuits are symmetric encryption keys.

12. The system of claim 9, wherein the power-distribution processing unit is further configured to:

discard at least one symbol of the plurality of symbols in response to a bit error rate for the at least one symbol being below the threshold error measure.

13. The system of claim 8, wherein being configured to compute the first measure of error includes being configured to use forward error correction data that is present in the first symbol.