Based sampling and binning for yield critical defects

• US 9,310,320 B2
• Filed: 04/11/2014
• Issued: 04/12/2016
• Est. Priority Date: 04/15/2013
• Status: Active Grant

• Current Assignee: KLA-Tencor Corporation
• Original Assignee: KLA-Tencor Corporation
• Inventors: Kurada, Satya, Babulnath, Raghav, Ng, Kwok, Gao, Lisheng
• Primary Examiner(s): Le, Vu
• Assistant Examiner(s): WOLDEMARIAM, AKLILU K
• Application Number:
  US14/251,415
• Publication Number:
  US 20140307947A1
• Time in Patent Office: 732 Days
• Field of Search: 382/149, 382/145, 382/144, 382/232, 382/264, 716/21, 716/55, 716/112, 702/81, 702/82, 702/179, 702/180, 702181-183
• US Class Current: 1/1
• CPC Class Codes: G01N 2021/95676 Masks, reticles, shadow masks
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/956 Inspecting patterns on the surface of objects contactless testing of electronic circuits G01R31/308; testing currency G07D; manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G01N 21/95607 using a comparative method
• CPC Class Codes: G01N 2201/06113 Coherent sources; lasers
• CPC Class Codes: G01N 2201/068 Optics, miscellaneous
• CPC Class Codes: G01N 2201/10 Scanning
• CPC Class Codes: G01N 2201/12 Circuits of general importance; Signal processing
• CPC Class Codes: G06T 2207/20081 Training; Learning
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0006 using a design-rule based approach
• CPC Class Codes: G06T 7/0008 checking presence/absence
• CPC Class Codes: G06T 7/001 using an image reference approach

Abstract

Methods and systems for design based sampling and binning for yield critical defects are provided. One method includes aligning each image patch in each inspection image frame generated for a wafer by an optical subsystem of an inspection system to design information for the wafer. The method also includes deriving multiple layer design attributes at locations of defects detected in the image patches. In addition, the method includes building a decision tree with the multiple layer design attributes. The decision tree is used to separate the defects into bins with different yield impacts on a device being formed on the wafer. The method also includes binning the defects with the decision tree.

Claims

1. A method for wafer inspection, comprising:

scanning a wafer with an inspection system thereby generating image patches in inspection image frames for the wafer, wherein the scanning step is performed with an optical subsystem of the inspection system;

aligning each of the image patches in each of the inspection image frames to design information for the wafer;

detecting defects in the image patches;

deriving multiple layer design attributes at locations of the defects from the image patches corresponding to the locations of the defects;

building a decision tree with the multiple layer design attributes, wherein the decision tree separates the defects into bins with different yield impacts on a device being formed on the wafer, and wherein the decision tree is built such that the defects that are one type of defects of interest and have a first of the different yield impacts are separated into a first of the bins and defects that are the one type of the defects of interest and have a second of the different yield impacts are separated into a second of the bins; and

binning the defects with the decision tree to thereby separate the defects into the bins with the different yield impacts on the device being formed on the wafer and to separate the one type of the defects of interest having the first of the different yield impacts into the first of the bins and the one type of the defects of interest having the second of the different yield impacts into the second of the bins, wherein the aligning, detecting, deriving, building, and binning steps are performed with one or more computer subsystems of the inspection system.

2. The method of claim 1, wherein the multiple layer design attributes comprise design attributes for a layer of the wafer for which the image patches are generated and at least one additional layer of the wafer formed before the layer.

3. The method of claim 1, wherein the multiple layer design attributes comprise design attributes for a layer of the wafer for which the image patches are generated and at least one additional layer of the wafer not yet formed on the wafer.

4. The method of claim 1, wherein said aligning comprises selecting an alignment site in each of the inspection image flames with both horizontal and vertical features.

5. The method of claim 1 , wherein said aligning comprises rendering simulated images from design data for the wafer that illustrate how the design data would appear in the image patches generated for the wafer by the inspection system, and wherein the design information comprises the rendered simulated images.

6. The method of claim 1, wherein the multiple layer design attributes comprise information for which areas of the wafer are NMOS and which areas of the wafer are PMOS.

7. The method of claim 1, wherein the multiple layer design attributes comprise information for which areas of the wafer are dummy areas and which areas of the wafer are not dummy areas.

8. The method of claim 1 , wherein the multiple layer design attributes comprise information for which areas of the wafer comprise dummy structures and which areas of the wafer comprise device structures.

9. The method of claim 1, wherein the multiple layer design attributes comprise information for which areas of the wafer comprise redundant structures and which areas of the wafer comprise non-redundant structures.

10. The method of claim 1, further comprising sampling the defects detected on the wafer based on results of the binning step.

11. The method of claim 1, further comprising monitoring the defects detected on the wafer based on results of the binning step.

12. The method of claim 1, wherein the method is performed inline during a fabrication process performed on the wafer.

13. The method of claim 1, further comprising binning defects detected on different wafers on which different devices are being formed with the decision tree.

14. The method of claim 1, further comprising binning defects detected on different wafers for which the scanning step was performed with different optics modes of the inspection system with the decision tree.

15. The method of claim 1, wherein the decision tree is independent of an optics mode of the inspection system used for the scanning.

16. The method of claim 1, further comprising determining an effect that the defects detected on the wafer have on yield of a fabrication process performed on the wafer based on results of the binning.

17. A non-transitory computer-readable medium, storing program instructions executable on a computer system of an inspection system for performing a computer-implemented method for wafer inspection, wherein the computer-implemented method comprises:

scanning a wafer with an inspection system thereby generating image patches in inspection image frames for the wafer, wherein the scanning step is performed with an optical subsystem of the inspection system;

aligning each of the image patches in each of the inspection image frames to design information for the wafer;

detecting defects in the image patches;

deriving multiple layer design attributes at locations of the defects from the image patches corresponding to the locations of the defects;

building a decision tree with the multiple layer design attributes, wherein the decision tree separates the defects into bins with different yield impacts on a device being formed on the wafer, and wherein the decision tree is built such that the defects that are one type of defects of interest and have a first of the different yield impacts are separated into a first of the bins and the defects that are the one type of the defects of interest and have a second of the different yield impacts are separated into a second of the bins; and

binning the defects with the decision tree to thereby separate the defects into the bins with the different yield impacts on the device being formed on the wafer and to separate the one type of the defects of interest having the first of the different yield impacts into the first of the bins and the one type of the defects of interest having the second of the different yield impacts into the second of the bins.

18. A wafer inspection system, comprising:

an optical subsystem configured to scan a wafer thereby generating image patches in inspection image frames for the wafer; and

one or more computer subsystems coupled to the optical subsystem, wherein the one or more computer subsystems are configured for;

aligning each of the image patches in each of the inspection image frames to design information for the wafer;

detecting defects in the image patches;

deriving multiple layer design attributes at locations of the defects from the image patches corresponding to the locations of the defects;

building a decision tree with the multiple layer design attributes, wherein the decision tree separates the defects into bins with different yield impacts on a device being formed on the wafer, and wherein the decision tree is built such that the defects that are one type of defects of interest and have a first of the different yield impacts are separated into a first of the bins and the defects that are the one type of the defects of interest and have a second of the different yield impacts are separated into a second of the bins; and

binning the defects with the decision tree to thereby separate the defects into the bins with the different yield impacts on the device being formed on the wafer and to separate the one type of the defects of interest having the first of the different yield impacts into the first of the bins and the one type of the defects of interest having the second of the different yield impacts into the second of the bins.

19. The wafer inspection system of claim 18, wherein the multiple layer design attributes comprise design attributes for a layer of the wafer for which the image patches are generated and at least one additional layer of the wafer formed before the layer.

20. The wafer inspection system of claim 18, wherein the multiple layer design attributes comprise design attributes for a layer of the wafer for which the image patches are generated and at least one additional layer of the wafer not vet formed on the wafer.

21. The wafer inspection system of claim 18, wherein said aligning comprises selecting an alignment site in each of the inspection image frames with both horizontal and vertical features.

22. The wafer inspection system of claim 18, wherein said aligning comprises rendering simulated images from design data for the wafer that illustrate how the design data would appear in the image patches generated for the wafer by the optical subsystem, and wherein the design information comprises the rendered simulated images.

23. The wafer inspection system of claim 18, wherein the multiple layer design attributes comprise information for which areas of the wafer are NMOS and which areas of the wafer are PMOS.

24. The wafer inspection system of claim 18, wherein the multiple layer design attributes comprise information for which areas of the wafer are dummy areas and which areas of the wafer are not dummy areas.

25. The wafer inspection system of claim 18, wherein the multiple layer design attributes comprise information for which areas of the wafer comprise dummy structures and which areas of the wafer comprise device structures.

26. The wafer inspection system of claim 18, wherein the multiple layer design attributes comprise information for which areas of the wafer comprise redundant structures and which areas of the wafer comprise non-redundant structures.

27. The wafer inspection system of claim 18, wherein the one or more computer subsystems are further configured for sampling the defects detected on the wafer based on results of the binning.

28. The wafer inspection system of claim 18, wherein the one or more computer subsystems are further configured for monitoring the defects detected on the wafer based on results of the binning.

29. The wafer inspection system of claim 18, wherein the one or more computer subsystems are further configured for performing the aligning, detecting, deriving, building, and binning inline during a fabrication process performed on the wafer.

30. The wafer inspection system of claim 18, wherein the one or more computer subsystems are further configured for binning defects detected on different wafers on which different devices are being formed with the decision tree.

31. The wafer inspection system of claim 18, wherein the one or more computer subsystems are further configured for binning defects detected on different wafers scanned with different optics modes of the optical subsystem with the decision tree.

32. The wafer inspection system of claim 18, wherein the decision tree is independent of an optics mode of the optical subsystem used for scanning the wafer.

33. The wafer inspection system of claim 18, wherein the one or more computer subsystems are further configured for determining an effect that the defects detected on the wafer have on yield of a fabrication process performed on the wafer based on results of the binning.