High speed tester communication interface between test slice and trays

• US 9,310,427 B2
• Filed: 07/24/2013
• Issued: 04/12/2016
• Est. Priority Date: 07/24/2013
• Status: Active Grant

• Current Assignee: Advantest Corporation
• Original Assignee: Advantest Corporation
• Inventors: Su, Mei-Mei, Kushnick, Eric, Wolff, Roland
• Primary Examiner(s): ALLGOOD, ALESA M
• Application Number:
  US13/950,164
• Publication Number:
  US 20150028908A1
• Time in Patent Office: 993 Days
• Field of Search: 324/750.05, 324/757.01, 324/750.3, 324/756.02, 324/762.01, 324/754.21, 324/762.03, 324/762.05
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/2889 Interfaces, e.g. between probe and tester G01R31/31905 and G01R1/07364 take precedence
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units
• CPC Class Codes: G11C 2029/5602 Interface to device under test
• CPC Class Codes: G11C 29/56012 Timing aspects, clock generation, synchronisation

Abstract

A tester system is disclosed. The tester system comprises a tester module operable to generate test signals for testing a plurality of DUTs. It also comprises a plurality of cables operable to communicatively couple the tester module with a tray comprising the plurality of DUTs through a thermal chamber wall interface. Further, it comprises a plurality of connectors in contact with the tray, wherein the plurality of connectors is operable to provide an interface between the plurality of cables and conductive traces on the tray, and further wherein each of the plurality of connectors is operable to pass a respective subset of the test signals to each DUT on the tray via the conductive traces.

Claims

1. A method for testing using an automated test equipment (ATE), said method comprising:

transmitting test signals generated by a tester module for testing a plurality of DUTs through a thermal chamber wall interface using a plurality of cables;

communicating said test signals to a tray comprising said plurality of DUTs using said plurality of cables, wherein said plurality of cables communicatively couple said tester module to said tray; and

passing a respective subset of said test signals to each DUT on said tray via one of a plurality of connectors in contact with said tray, wherein said plurality of connectors provide an interface between said plurality of cables and conductive traces on said tray, and wherein said plurality of connectors make contact with a bottom of said tray using a spring mechanism, wherein said spring mechanism is operable to push up on said tray to allow said plurality of connectors to make contact with said tray.

2. The method of claim 1, wherein said tester module comprises FPGA components operable to generate a subset of said test signals.

3. The method of claim 1, wherein said plurality of cables comprise twinaxial cables operable to transmit high speed signals.

4. The method of claim 1, wherein said tray comprises a printed circuit board and a stiffener, wherein said printed circuit board comprises sockets for plugging in a plurality of DUTs.

5. The method of claim 1, wherein each of said plurality of connectors comprises:

an interposer operable to communicatively couple said test signals with pads on said tray;

a connector operable to receive said test signals through said plurality of cables; and

a printed circuit board for interfacing said interposer with said connector.

6. The method of claim 1, wherein a DUT on said tray receives test signals from a respective connector in closest proximity to said DUT.

7. The method of claim 1, wherein said plurality of DUTs are stacked horizontally on said tray with respect to said thermal chamber wall.

8. The method of claim 1, wherein said test signals are selected from a group consisting of:

serial signals, input/output (I/O) signals, and reference clocks.

9. The method of claim 8, wherein said serial signals comprise high speed serial signals.

10. A tester system comprising:

a tester module operable to generate test signals for testing a plurality of DUTs;

a plurality of cables operable to communicatively couple said tester module with a tray comprising said plurality of DUTs through a thermal chamber wall interface; and

a plurality of connectors in contact with said tray, wherein said plurality of connectors is operable to provide an interface between said plurality of cables and conductive traces on said tray, and further wherein each of said plurality of connectors is operable to pass a respective subset of said test signals to each DUT on said tray via said conductive traces and wherein said plurality of connectors make contact with a bottom of said tray using a spring mechanism, wherein said spring mechanism is operable to push up on said tray to allow said plurality of connectors to make contact with said tray.

11. The system of claim 10, wherein said tray is operable to be disconnected from said tester module by uncoupling connective pads on said tray from interposers associated with said plurality of connectors.

12. The system of claim 10, wherein said tester module comprises FPGA components operable to generate a subset of said test signals.

13. The system of claim 10, wherein said plurality of cables comprise twinaxial cables operable to transmit high speed signals.

14. The system of claim 10, wherein said tray comprises a printed circuit board and a stiffener, wherein said printed circuit board comprises sockets for plugging in a plurality of DUTs.

15. The system of claim 10, wherein each of said plurality of connectors comprises:

an interposer operable to communicatively couple said test signals with pads on said tray;

a connector operable to receive said test signals through said plurality of cables; and

a printed circuit board for interfacing said interposer with said connector.

16. The system of claim 10, wherein a DUT on said tray receives test signals from a respective connector in closest proximity to said DUT.

17. The system of claim 10, wherein said plurality of DUTs are stacked horizontally on said tray with respect to said thermal chamber wall.

18. The system of claim 10, wherein said test signals are selected from a group consisting of:

serial signals, input/output (I/O) signals, and reference clocks.

19. The system of claim 18, wherein said serial signals comprise high speed serial signals.

20. A test equipment apparatus comprising:

a tester tray comprising sockets operable to communicatively couple said tester tray with a plurality of DUTs; and

a plurality of connectors in contact with said tester tray, wherein said plurality of connectors is operable to provide an interface between test signals received via cables and conductive pads on said tester tray, and wherein each of said plurality of connectors is operable to pass a respective subset of said test signals to each DUT on said tester tray via said conductive pads and wherein said plurality of connectors make contact with a bottom of said tray using a spring mechanism, wherein said spring mechanism is operable to push up on said tray to allow said plurality of connectors to make contact with said tray, and

further wherein each connector from said plurality of connectors comprises;

an interposer operable to communicatively couple said test signals with pads on said tray;

a connector operable to receive said test signals through said cables; and

a printed circuit board for interfacing said interposer with said connector.