Instruction that specifies an application thread performance state
First Claim
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1. An apparatus, comprising:
- a processor having;
a processing core to execute an instruction that specifies a performance state of an application thread, said instruction belonging to said application thread;
a first register to store said performance state;
a second register to store a system edict value to indicate whether the processor is biased toward higher performance and higher power consumption or lower performance and lower power consumption; and
power management control logic coupled to the first register and the second register to set a performance state of the processing core as a function of said performance state of said application thread and said system edict value.
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Abstract
An apparatus is described that includes a processor. The processor has a processing core to execute an instruction that specifies a performance state of an application thread. The instruction belongs to the application thread. The processor includes a register to store the performance state. The processor includes power management control logic coupled to the register to set a performance state of the processing core as a function of the performance state.
36 Citations
20 Claims
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1. An apparatus, comprising:
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a processor having; a processing core to execute an instruction that specifies a performance state of an application thread, said instruction belonging to said application thread; a first register to store said performance state; a second register to store a system edict value to indicate whether the processor is biased toward higher performance and higher power consumption or lower performance and lower power consumption; and power management control logic coupled to the first register and the second register to set a performance state of the processing core as a function of said performance state of said application thread and said system edict value. - View Dependent Claims (2, 3, 4, 5, 6, 20)
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7. A method, comprising:
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executing on a processing core of a processor an instruction that specifies a performance state of a thread of an application, said instruction belonging to said thread; writing said performance state of said thread to register space; providing a system edict value that indicates whether the processor is biased toward higher performance and higher power consumption or lower performance and lower power consumption; accessing said performance state of said thread from said register space; and changing a performance state of said processing core consistent with said performance state as a function of said performance state of said thread and said system edict value. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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14. A non-transitory machine readable medium containing program code that when processed by a processor causes a method to be performed, said method comprising:
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executing on a processing core of the processor an instruction that specifies a performance state of a thread of an application, said instruction belonging to said thread; writing said performance state of said thread to register space; providing a system edict value that indicates whether the processor is biased toward higher performance and higher power consumption or lower performance and lower power consumption; accessing said performance state of said thread from said register space; and changing a performance state of said processing core consistent with said performance state as a function of said performance state of said thread and said system edict value. - View Dependent Claims (15, 16, 17, 18, 19)
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Specification