Dynamic address negotiation for shared memory regions in heterogenous multiprocessor systems

• US 9,311,011 B2
• Filed: 08/07/2013
• Issued: 04/12/2016
• Est. Priority Date: 08/07/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Gathala, Sudha Anil Kumar, Ermolinskiy, Andrey, Vick, Christopher A.
• Primary Examiner(s): Shah, Sanjiv
• Assistant Examiner(s): Waddy, Jr., Edward
• Application Number:
  US13/961,085
• Publication Number:
  US 20150046661A1
• Time in Patent Office: 979 Days
• Field of Search: 711/E12.001, 711/E12.059, 711/E12.068, 711/147, 711/153, 711/154, 711/167, 711/202, 709/215, 709/218, 709/230, 709/213, 709/1, 718/1, 718/100, 718/102, 718/108
• US Class Current: 1/1
• CPC Class Codes: G06F 12/023 Free address space management
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0671 In-line storage system
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Mobile computing devices may be configured to compile and execute portions of a general purpose software application in an auxiliary processor (e.g., a DSP) of a multiprocessor system by reading and writing information to a shared memory. A first process (P1) on the applications processor may request address negotiation with a second process (P2) on the auxiliary processor, obtain a first address map from a first operating system, and send the first address map to the auxiliary processor. The second process (P2) may receive the first address map, obtain a second address map from a second operating system, identify matching addresses in the first and second address maps, store the matching addresses as common virtual addresses, and send the common virtual addresses back to the applications processor. The first and second processes (i.e., P1 and P2) may each use the common virtual addresses to map physical pages to the memory.

Claims

1. A method of providing access to a shared memory region of a multiprocessor computing device having a first processing core and a second processing core, the method comprising:

requesting, by a first process in the first processing core, address negotiation with a second process in the second processing core;

obtaining a first address map of the first process in the first processing core in response to requesting address negotiation with the second process in the second processing core;

sending the first address map to the second processing core so as to cause the second processing core to obtain a second address map of the second process in the second processing core;

receiving a common virtual address in the first processing core in response to sending the first address map to the second processing core, the received common virtual address including an address included in both the first address map of the first process and the second address map of the second process;

storing the received common virtual address as a first attribute of the shared memory region inside a first operating system kernel of the first processing core; and

mapping the shared memory region at the received common virtual address of the first process.

2. The method of claim 1, further comprising:

performing address matching operations in the second processing core to determine whether the first and second address maps include a matching virtual address;

storing the matching virtual address as the common virtual address and as a second attribute of the shared memory region of a second operating system kernel of the second processing core;

sending the common virtual address to the first processing core; and

mapping physical pages of the shared memory region at the common virtual address for the second process in the second processing core.

3. The method of claim 2, wherein each of the first and second processing cores includes a hardware memory management unit (MMU).

4. The method of claim 2, wherein receiving the first address map in the second processing core comprises receiving the first address map in an address negotiation handler thread of the second processing core.

5. A multiprocessor computing device, comprising:

means for requesting by a first process in a first processing core address negotiation with a second process in a second processing core;

means for obtaining a first address map of the first process in the first processing core in response to requesting address negotiation with the second process in the second processing core;

means for sending the first address map to the second processing core so as to cause the second processing core to obtain a second address map of the second process in the second processing core;

means for receiving a common virtual address in the first processing core in response to sending the first address map to the second processing core, the received common virtual address including an address included in both the first address map of the first process and the second address map of the second process;

means for storing the received common virtual address as a first attribute of a shared memory region inside a first operating system kernel of the first processing core; and

means for mapping the shared memory region at the received common virtual address of the first process.

6. The multiprocessor computing device of claim 5, further comprising

means for performing address matching operations in the second processing core to determine whether the first and second address maps include a matching virtual address;

means for storing the matching virtual address as the common virtual address and as a second attribute of the shared memory region of a second operating system kernel of the second processing core;

means for sending the common virtual address to the first processing core; and

means for mapping physical pages of the shared memory region at the common virtual address for the second process in the second processing core.

7. The multiprocessor computing device of claim 6, wherein means for receiving the first address map in the second processing core comprises means for receiving the first address map in an address negotiation handler thread of the second processing core.

8. A multiprocessor computing device, comprising:

a first processing core;

a second processing core; and

a shared memory region coupled to the first and second processing cores, wherein the first processing core is configured with processor-executable instructions to perform operations comprising;

requesting by a first process address negotiation with a second process in the second processing core;

obtaining a first address map of the first process in response to requesting address negotiation with the second process in the second processing core;

sending the first address map to the second processing core so as to cause the second processing core to obtain a second address map of the second process in the second processing core;

receiving a common virtual address in response to sending the first address map to the second processing core, the received common virtual address including an address included in both the first address map of the first process and the second address map of the second process;

storing the received common virtual address as a first attribute of the shared memory region inside a first operating system kernel; and

mapping the shared memory region at the received common virtual address of the first process.

9. The multiprocessor computing device of claim 8, wherein the second processing core is configured with processor-executable instructions to perform operations comprising:

performing address matching operations to determine whether the first and second address maps include a matching virtual address;

storing the matching virtual address as the common virtual address and as a second attribute of the shared memory region of a second operating system kernel;

sending the common virtual address to the first processing core; and

mapping physical pages of the shared memory region at the common virtual address for the second process.

10. The multiprocessor computing device of claim 9, wherein each of the first and second processing cores includes a hardware memory management unit (MMU).

11. The multiprocessor computing device of claim 9, wherein the second processing core is configured with processor-executable instructions to perform operations such that receiving the first address map comprises receiving the first address map in an address negotiation handler thread.

12. A non-transitory computer readable storage medium having stored thereon processor-executable software instructions configured to cause a first processing core of a multiprocessor computing device to perform operations comprising:

requesting by a first process address negotiation with a second process in a second processing core of the multiprocessor computing device;

obtaining a first address map of the first process in response to requesting address negotiation with the second process in the second processing core;

sending the first address map to the second processing core so as to cause the second processing core to obtain a second address map of the second process in the second processing core;

receiving a common virtual address in response to sending the first address map to the second processing core, the received common virtual address including an address included in both the first address map of the first process and the second address map of the second process;

storing the received common virtual address as a first attribute of a shared memory region inside a first operating system kernel; and

mapping the shared memory region at the received common virtual address of the first process.

13. The non-transitory computer readable storage medium of claim 12, wherein the stored processor-executable software instructions are configured to cause the second processing core of the multiprocessor computing device to perform operations comprising:

performing address matching operations to determine whether the first and second address maps include a matching virtual address;

storing the matching virtual address as the common virtual address and as a second attribute of the shared memory region of a second operating system kernel;

sending the common virtual address to the first processing core; and

mapping physical pages of the shared memory region at the common virtual address for the second process.

14. The non-transitory computer readable storage medium of claim 13, wherein the stored processor-executable software instructions are configured to cause the second processing core of the multiprocessor computing device to perform operations such that receiving the first address map comprises receiving the first address map in an address negotiation handler thread.