Demote instruction for relinquishing cache line ownership

• US 9,311,238 B2
• Filed: 06/18/2014
• Issued: 04/12/2016
• Est. Priority Date: 12/12/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation, International Business Machines SA (International Business Machines Corporation)
• Original Assignee: International Business Machines Corporation
• Inventors: Shum, Chung-Lung Kevin, Jackson, Kathryn Marie, Webb, Charles Franklin
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US14/308,140
• Publication Number:
  US 20140304471A1
• Time in Patent Office: 664 Days
• Field of Search: 711/121, 711/141, 711/144, 711/145
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0833 in combination with broadcast means (e.g. for invalidation or updating)
• CPC Class Codes: G06F 12/0837 with software control, e.g. non-cacheable data
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0842 for multiprocessing or multitasking
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/314 In storage network, e.g. network attached cache
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/6042 Allocation of cache space to multiple users or processors
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 3/0614 Improving the reliability of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A computer system microprocessor core having a cache subsystem executes a demote instruction to cause an exclusively owned demote instruction specified cache line owned by the same microprocessor core to be shared or read-only.

Claims

1. A method for relinquishing cache ownership of a cache line, the method comprising executing, by a selected processor of a multi-processor system, a demote instruction, the demote instruction specifying a logical address, the multi-processor system comprising a multi-cache system and a cache coherency ownership scheme for providing any one of shared ownership and exclusive ownership of a cache line to caches of the multi-processor system, an exclusively owned cache line configured to be accessible, by a processor, in only one cache of the multi-cache system, the only one cache having the exclusively owned cache line, a shared ownership cache line configured to be accessible, by processors, in a plurality of caches of the multi-cache system, the plurality of caches having the shared ownership cache line, the executing the demote instruction performing a method comprising:

based on the specified logical address, determining whether a cache line of the cache system, is exclusively owned by a selected cache of the selected processor;

based on determining that the cache line is exclusively owned by the selected cache of the selected processor, relinquishing, by the selected cache, exclusive ownership of the cache line; and

based on executing the demote instruction, the selected processor completes all pending stores before relinquishing the exclusive ownership of the cache line, wherein the relinquishing the exclusive ownership of the cache line comprises setting the ownership of the cache line of the selected cache to any one of shared ownership or read-only allowing a processor of the multiprocessor system to immediately be given exclusive ownership to that cache line without waiting on any processor'"'"'s explicit cross invalidate acknowledgement, and wherein execution of the demote instruction performs no architectural update.

2. The method according to claim 1, further comprising translating the logical address to a cache address.

3. The method according to claim 2, wherein the cache address is an absolute address.

4. The method according to claim 2, wherein the selected processor is an out-of-order processor.

5. The method according to claim 1, wherein the caches of the multi-cache system consist of a plurality of private caches, wherein each processor of the multi-processor system comprises an associated private cache of the multi-cache system, wherein the selected cache is a selected private cache, wherein the determining is performed on the selected private cache associated with the selected processor.

6. The method according to claim 1, further comprising:

prior to the executing the demote instruction, obtaining, by the selected cache, ownership of the cache line in a private cache of the selected processor from a private cache of another processor of the multi-processor system.

7. The method according to claim 1, wherein the relinquishing, by the selected processor, exclusive ownership of the cache line, causes the cache line to be in a shared ownership state in a private cache of the selected processor, the method further comprising:

subsequent to the executing the demote instruction, obtaining shared ownership of the cache line by another private cache of the multiprocessor system.

8. The method according to claim 1, wherein the demote instruction is an instruction of any one of an operating system, a device driver or an application that uses common blocks.

9. A system for relinquishing cache ownership of a cache line, the system comprising:

a selected private cache; and

a selected processor of a multi-processor system, the selected processor communicatively coupled to said selected private cache, each processor of the multi-processor system comprising an associated private cache of a multi-cache system, the multi-cache system comprising a cache coherency ownership scheme configured to provide any one of shared ownership and exclusive ownership of a cache line to private caches of the multi-cache system, an exclusively owned cache line configured to be accessible, by a processor, in only one cache of the multi-cache system, the only one cache having the exclusively owned cache line, a shared ownership cache line configured to be accessible, by processors, in a plurality of caches of the multi-cache system, the plurality of caches having the shared ownership cache line, the selected processor configured to perform a method, the method comprising executing, by the selected processor of a multi-processor system, a demote instruction, the demote instruction specifying a logical address, the executing the demote instruction performing a method comprising;

based on the specified logical address, determining whether a cache line of the selected private cache, is exclusively owned by the selected private cache of the selected processor;

based on determining that the cache line is exclusively owned by the selected private cache, relinquishing, by the selected private cache, exclusive ownership of the cache line; and

based on executing the demote instruction, the selected processor completes all pending stores before relinquishing the exclusive ownership of the cache line, wherein the relinquishing the exclusive ownership of the cache line comprises setting the ownership of the cache line of the selected cache to any one of shared ownership or read-only allowing a processor of the multiprocessor system to immediately be given exclusive ownership to that cache line without waiting on any processor'"'"'s explicit cross invalidate acknowledgement, and wherein execution of the demote instruction performs no architectural update.

10. The system according to claim 9, further comprising translating the logical address to a cache address.

11. The system according to claim 10, wherein the cache address is an absolute address.

12. The system according to claim 10, wherein the selected processor is an out-of-order processor.

13. The system according to claim 9, further comprising:

prior to the executing the demote instruction, obtaining by the selected processor, ownership of the cache line in the private cache of the selected processor from a private cache of another processor of the multi-processor system.

14. The system according to claim 9, wherein the relinquishing, by the selected processor, exclusive ownership of the cache line, causes the cache line to be in a shared ownership state in the selected private cache of the selected processor, the method further comprising:

subsequent to the executing the demote instruction, obtaining shared ownership of the cache line by another private cache of the multiprocessor system.