Methods for memory management in parallel networks

• US 9,311,596 B2
• Filed: 03/05/2014
• Issued: 04/12/2016
• Est. Priority Date: 09/21/2011
• Status: Expired due to Fees

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm Technologies Incorporated (Qualcomm, Inc.)
• Inventors: Szatmary, Botond, Petre, Csaba, Izhikevich, Eugene M., Kimball, Robert Howard, Wegrzyn, Jan Krzys, Canoy, Michael-David Nakayoshi, Piekniewski, Filip
• Primary Examiner(s): Hill, Stanley K
• Assistant Examiner(s): BROWN JR, NATHAN H
• Application Number:
  US14/198,550
• Publication Number:
  US 20140250037A1
• Time in Patent Office: 769 Days
• Field of Search: 706/10
• US Class Current: 1/1
• CPC Class Codes: G06N 3/04 Architecture, e.g. interconnection topology
• CPC Class Codes: G06N 3/049 Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
• CPC Class Codes: G06N 3/088 Non-supervised learning, e.g. competitive learning
• CPC Class Codes: G06N 3/10 Interfaces, programming languages or software development kits, e.g. for simulating neural networks

Abstract

A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. Methods for managing memory in a processing system are described whereby memory can be allocated among a plurality of elements and rules configured for each element such that the parallel execution of the spiking networks is most optimal.

Claims

1. A method for managing memory in a processing system, comprising:

allocating memory among a plurality of elements;

configuring rules for individual elements, wherein at least a portion of the rules associated with a first element type is configured to control updates to memory allocated to a second element type; and

providing a system clock defining a step interval during which one or more rules associated with individual elements are executed;

wherein;

the plurality of elements are interconnected according to a graph representative of a neuronal network;

execution of a portion of the rules associated with two or more elements of a given type is independent of an order of configuration during the step interval, the given type comprising one of the first element type or the second element type; and

memory of a given element having the allocated memory is updated consistent with a rule of the one or more rules configured for the given element.

2. The method of claim 1 wherein the plurality of elements comprises:

a plurality of units, individual units characterized by a unit memory of the allocated memory; and

a plurality of doublets, individual doublets associated with a presynaptic unit and a postsynaptic unit; and

an individual doublet is operable to modify a postsynaptic unit memory.

3. The method of claim 2, wherein the modification of the postsynaptic unit memory is configured based on an event associated with the presynaptic unit.

4. The method of claim 3, wherein:

the modification of the postsynaptic unit memory is configured based on a doublet event rule of the one or more rules; and

detection of the event by the individual doublet is configured to trigger execution of the doublet event rule.

5. The method of claim 4, wherein:

the event is based on data within a presynaptic unit memory, the event being characterized by a time value; and

execution if the doublet event rule is delayed relative the time value.

6. The method of claim 3, wherein:

order of execution of one or more doublet event rules associated with one or more doublets of the plurality of doublets is arbitrary during a given step interval.

7. The method of claim 3, wherein:

the modification of the postsynaptic unit memory comprises an atomic addition operation.

8. A method of updating memory of distributed elements in a parallel processing system comprising a plurality of components, the method comprising:

based on an evaluation of memory of a first component of the plurality of components;

communicating to a second component via a third component of the plurality of components, information related to the first component;

based on the information, updating content of the third component memory in accordance with a first rule; and

based on the information, updating content of the second component memory in accordance with a second rule;

wherein;

individual ones of the first and the third components are operable to modify their own memory;

individual ones of the first and the third components comprise a computational unit and individual ones of the first and the third components are operable to modify their own memory;

the second component comprises an adaptable data interface between the first and the third components and operation of the second component in accordance with the second rule is configured to cause modification of the second component memory and the third component memory; and

the information comprises time of an event produced by the computational unit of the first component based on the evaluation.

9. The method of claim 8, wherein:

the evaluation is configured to determine a condition change associated with the first component;

the information comprises a first time value associated with the condition change;

execution of the first rule is triggered by the second component; and

the third component memory content update is configured based on the first time value.

10. The method of claim 9, wherein the modification of the second component memory is configured to occur after a delay relative the first time value.

11. The method of claim 9, wherein:

the second component memory update is configured based on the first time value; and

the second component memory update is configured to effectuate an adaptability of the adaptable data interface.

12. The method of claim 11, wherein:

the second component memory content update is configured based on a second time value of a second condition change condition change associated with the third component, the second condition change being determined based on a second evaluation of memory of the third component by the computational unit of the third component; and

the second evaluation is configured based on a value stored in the second component memory.

13. The method of claim 12, wherein the value is being produced by the second component memory update.

14. The method of claim 9, wherein:

the plurality of components comprises a plurality of adaptable data interfaces between the first component and a portion of the plurality of components, the plurality of adaptable data interfaces comprising the interface; and

a given data interface of the plurality of adaptable data interfaces is characterized by respective data interface memory configured to be updated in accordance with the second rule associated with the given data interface.

15. The method of claim 14, wherein execution of a plurality of the second rules associated with the plurality of data interfaces is configured to be delayed relative the first time value.

16. The method of claim 14, wherein:

execution of a plurality of the second rules associated with the plurality of data interfaces is order independent from one another; and

duration of a delay is configured independent for individual ones of the plurality of data interfaces.

17. The method of claim 14, wherein:

individual components of the portion of the plurality of components are characterized by memory configured to be updated in accordance with the first rule; and

execution of a plurality of the first rules associated with the portion of the plurality of components is order independent from one another.

18. The method of claim 8, wherein:

the evaluation is configured to determine a condition change associated with the first component;

the second rule comprises a first portion configured to effectuate the second component memory modification; and

execution of the first portion is triggered by the determination of the condition change.

19. A method of configuring a semiconductor integrated circuit for contemporaneous execution of a plurality of memory updates, the method comprising:

a plurality of elements, a given element having a memory configured to be updated according to a rule configured for the given element; and

a system clock defining a series of step intervals in which updates to memories of a first set of the elements are initiated and in which updates to memories of a second set of the elements are completed;

wherein;

the plurality of elements includes units and doublets, individual unit operable to modify its own memory, and individual doublet operable to modify its own memory and the memory of a unit; and

the updates to the memories of the second set of the elements include delayed updates.