Methods for memory management in parallel networks
First Claim
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1. A method for managing memory in a processing system, comprising:
- allocating memory among a plurality of elements;
configuring rules for individual elements, wherein at least a portion of the rules associated with a first element type is configured to control updates to memory allocated to a second element type; and
providing a system clock defining a step interval during which one or more rules associated with individual elements are executed;
wherein;
the plurality of elements are interconnected according to a graph representative of a neuronal network;
execution of a portion of the rules associated with two or more elements of a given type is independent of an order of configuration during the step interval, the given type comprising one of the first element type or the second element type; and
memory of a given element having the allocated memory is updated consistent with a rule of the one or more rules configured for the given element.
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Abstract
A simple format is disclosed and referred to as Elementary Network Description (END). The format can fully describe a large-scale neuronal model and embodiments of software or hardware engines to simulate such a model efficiently. The architecture of such neuromorphic engines is optimal for high-performance parallel processing of spiking networks with spike-timing dependent plasticity. Methods for managing memory in a processing system are described whereby memory can be allocated among a plurality of elements and rules configured for each element such that the parallel execution of the spiking networks is most optimal.
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Citations
19 Claims
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1. A method for managing memory in a processing system, comprising:
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allocating memory among a plurality of elements; configuring rules for individual elements, wherein at least a portion of the rules associated with a first element type is configured to control updates to memory allocated to a second element type; and providing a system clock defining a step interval during which one or more rules associated with individual elements are executed; wherein; the plurality of elements are interconnected according to a graph representative of a neuronal network; execution of a portion of the rules associated with two or more elements of a given type is independent of an order of configuration during the step interval, the given type comprising one of the first element type or the second element type; and memory of a given element having the allocated memory is updated consistent with a rule of the one or more rules configured for the given element. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of updating memory of distributed elements in a parallel processing system comprising a plurality of components, the method comprising:
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based on an evaluation of memory of a first component of the plurality of components; communicating to a second component via a third component of the plurality of components, information related to the first component; based on the information, updating content of the third component memory in accordance with a first rule; and based on the information, updating content of the second component memory in accordance with a second rule; wherein; individual ones of the first and the third components are operable to modify their own memory; individual ones of the first and the third components comprise a computational unit and individual ones of the first and the third components are operable to modify their own memory; the second component comprises an adaptable data interface between the first and the third components and operation of the second component in accordance with the second rule is configured to cause modification of the second component memory and the third component memory; and the information comprises time of an event produced by the computational unit of the first component based on the evaluation. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of configuring a semiconductor integrated circuit for contemporaneous execution of a plurality of memory updates, the method comprising:
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a plurality of elements, a given element having a memory configured to be updated according to a rule configured for the given element; and a system clock defining a series of step intervals in which updates to memories of a first set of the elements are initiated and in which updates to memories of a second set of the elements are completed; wherein; the plurality of elements includes units and doublets, individual unit operable to modify its own memory, and individual doublet operable to modify its own memory and the memory of a unit; and the updates to the memories of the second set of the elements include delayed updates.
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Specification