Memory module

• US 9,311,976 B2
• Filed: 10/26/2014
• Issued: 04/12/2016
• Est. Priority Date: 04/24/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Tsern, Ely K., Perego, Richard E., Hampel, Craig E.
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US14/523,922
• Publication Number:
  US 20150043290A1
• Time in Patent Office: 534 Days
• Field of Search: 365/194, 365/191, 365/193, 365/233.1, 365/221
• US Class Current: 1/1
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory module having integrated circuit (IC) components, a termination structure, an address/control signal path, a clock signal path, multiple data signal paths and multiple strobe signal paths. The strobe signal paths and data signal paths are coupled to respective IC components, and the address/control signal path and clock signal path are coupled in common to all the IC components. The address/control signal path extends along the IC components to the termination structure such that control signals propagating toward the termination structure arrive at address/control inputs of respective IC components at progressively later times corresponding to relative positions of the IC components.

Claims

1. A memory module comprising:

a circuit board;

a first plurality of integrated circuit (IC) components disposed on the circuit board, each of the IC components having an address/control input, a clock input, a data output and a strobe output;

a termination structure disposed on the circuit board;

an address/control signal path coupled at one end to the termination structure and coupled to the address/control input of each of the IC components such that control signals propagating toward the termination structure on the address/control signal path arrive at the address/control inputs of respective IC components at progressively later times corresponding to relative positions of the IC components;

a clock signal path coupled to the clock input of each of the IC components such that a clock signal propagating on the clock signal path arrives at the clock inputs of respective IC components at progressively later times corresponding to the times at which the control signals arrive at the address/control inputs of the IC components, the clock signal indicating to the IC components respective times at which to sample the control signals arriving at their address/control inputs;

a plurality of data signal paths, each of the data signal paths extending from the data output of a respective one of the IC components to an edge of the circuit board and including a plurality of data signal conductors to convey a respective read data value; and

a plurality of strobe signal paths, each of the strobe signal paths extending from the strobe output of a respective one of the IC components to the edge of the circuit board, each of the strobe signal paths to convey a strobe signal that indicates that the read data value is present on the data signal path extending from the data output of the one of the IC components.

2. The memory module of claim 1 wherein the address/control signal path extends from the edge of the circuit board to the termination structure.

3. The memory module of claim 1 wherein the clock signal path extends from the edge of the circuit board and is coupled along its length to the clock input of each of the IC components.

4. The memory module of claim 1 wherein the plurality of IC components comprises a plurality of dynamic random access memory (DRAM) devices.

5. The memory module of claim 1 wherein the control signals comprise signals indicating that a respective read operation is to be performed within each of the IC components, the read operation including output of the read data value via the data output of the IC component.

6. The memory module of claim 1 wherein the address/control signal path comprises a plurality of signal conductors to convey an address value during a first interval and to convey a read command corresponding to the address value during a second interval.

7. The memory module of claim 1 wherein each of the IC components comprises receive circuitry to receive address information via the address/control signal path and control information via the address/control signal path.

8. The memory module of claim 1 wherein the clock signal path is routed alongside and parallel to the address/control signal path.

9. The memory module of claim 1 further comprising a second plurality of IC components disposed on the circuit board, the IC components of the second plurality being coupled in parallel to the address/control signal path and each coupled to a respective one of the data signal paths and to a respective one of the strobe signal paths.

10. The memory module of claim 1 further comprising a second plurality of IC components coupled respectively to the data signal paths, the clock signal path being coupled along its length to respective clock inputs of the IC components of the second plurality such that the clock signal propagating on the clock signal path arrives at the clock input of each IC component of the second plurality at a progressively later times.

11. A memory module comprising:

a circuit board;

a first plurality of integrated circuit (IC) components disposed on the circuit board, each of the IC components having an address/control input, a clock input, a data input and a strobe input;

a termination structure disposed on the circuit board;

an address/control signal path coupled at one end to the termination structure and coupled to the address/control input of each of the IC components such that control signals propagating toward the termination structure on the address/control signal path arrive at the address/control inputs of respective IC components at progressively later times corresponding to relative positions of the IC components;

a clock signal path coupled to the clock input of each of the IC components such that a clock signal propagating on the clock signal path arrives at the clock inputs of respective IC components at progressively later times corresponding to the times at which the control signals arrive at the address/control inputs of the IC components, the clock signal indicating to the IC components respective times at which to sample the control signals arriving at their address/control inputs;

a plurality of data signal paths, each of the data signal paths extending from the data input of a respective one of the IC components to an edge of the circuit board and including a first plurality of data signal conductors to convey a write data value to the one of the IC components and at least one mask signal conductor to convey a write mask signal that indicates whether the write data value is to be stored within the one of the IC components; and

a plurality of strobe signal paths, each of the strobe signal paths extending from the edge of the circuit board to the strobe input of a respective one of the IC components to convey a strobe signal that indicates presence of the write data value on the data signal path coupled to the data input of the respective one of the IC components.

12. The memory module of claim 11 wherein the address/control signal path extends from the edge of the circuit board to the termination structure.

13. The memory module of claim 11 wherein the clock signal path extends from the edge of the circuit board and is coupled along its length to the clock input of each of the IC components.

14. The memory module of claim 11 wherein the plurality of IC components comprises a plurality of dynamic random access memory (DRAM) devices.

15. The memory module of claim 11 wherein the control signals comprise signals indicating that a respective write operation is to be performed within each of the IC components, the write operation including receipt of the write data value via the data input of the IC component.

16. The memory module of claim 11 wherein the address/control signal path comprises a plurality of signal conductors to convey an address value during a first interval and to convey a write command corresponding to the address value during a second interval.

17. The memory module of claim 11 wherein each of the IC components comprises receive circuitry to receive address information via the address/control signal path and control information via the address/control signal path.

18. The memory module of claim 11 wherein the clock signal path is routed alongside and parallel to the address/control signal path.

19. The memory module of claim 11 further comprising a second plurality of IC components disposed on the circuit board, the IC components of the second plurality being coupled in parallel to the address/control signal path and each coupled to a respective one of the data signal paths and to a respective one of the strobe signal paths .

20. The memory module of claim 11 further comprising a second plurality of IC components coupled respectively to the data signal paths, the clock signal path being coupled along its length to respective clock inputs of the IC components of the second plurality such that the clock signal propagating on the clock signal path arrives at the clock input of each IC component of the second plurality at a progressively later times.