Methods for forming FinFETS having a capping layer for reducing punch through leakage

• US 9,312,183 B1
• Filed: 11/03/2014
• Issued: 04/12/2016
• Est. Priority Date: 11/03/2014
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Kim, Hoon, Sung, Min Gyu
• Primary Examiner(s): Tran, Thanh Y
• Application Number:
  US14/531,743
• Publication Number:
  US 20160126141A1
• Time in Patent Office: 526 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7854 with rounded corners

Abstract

A method for forming FinFETs having a capping layer for reducing punch through leakage includes providing an intermediate semiconductor structure having a semiconductor substrate and a fin disposed on the semiconductor substrate. A capping layer is disposed over the fin, and an isolation fill is disposed over the capping layer. A portion of the isolation fill and the capping layer is removed to expose an upper surface portion of the fin. Tapping layer and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layer operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layer.

Claims

1. A method comprising:

providing an intermediate semiconductor structure comprising;

a semiconductor substrate;

a fin disposed on the semiconductor substrate;

providing a first capping layer disposed over the fin;

providing first isolation fill disposed over the capping layer;

removing a portion of the first isolation fill and the first capping layer to expose an upper surface portion of the fin;

providing a second capping layer disposed over the exposed fin, and a second isolation fill over the second capping layer, the second capping layer being different from the first capping layer;

removing a portion of the second capping layer and second isolation fill to expose an upper surface of the fin; and

wherein the capping layers and a lower portion of the fin define an interface dipole layer barrier, a portion of the capping layers operable to provide an increased negative charge or an increased positive charge adjacent to the fin, to reduce punch-through leakage compared to a fin without the capping layers.

2. The method of claim 1 wherein the first capping layer comprises a thickness of about 0.5 nanometers.

3. The method of claim 1 wherein the providing a first capping layer over the fin comprise providing the capping layer using atomic layer deposition or chemical vapor deposition.

4. The method of claim 1 wherein the first capping layer comprises an oxide, and the fin comprise silicon, silicon-germanium, or pure germanium.

5. The method of claim 1 wherein the first capping layer comprises aluminum oxide, titanium dioxide, zirconium dioxide, hafnium oxide, magnesium oxide, strontium oxide, lanthanum oxide, lutetium oxide, yttrium oxide, or germanium oxide.

6. The method of claim 1 wherein the removing a portion of the first isolation fill comprises densification and chemical mechanical planarization.

7. The method of claim 1 further comprising forming a gate disposed over the upper portion of the fin.

8. A method comprising:

providing a semiconductor substrate and a plurality of fins disposed on the semiconductor substrate;

providing a first capping layer disposed over the fins, and a first isolation fill disposed over the first capping layer;

removing a portion of the capping layer and the first isolation fill to expose some of the fins;

providing a second capping layer disposed over the exposed fins, and a second isolation fill over the second capping layer, the second capping layer being different from the first capping layer;

removing a portion of the first and second capping layers and the first and second isolation fills to expose upper surface portions of the fins; and

wherein the capping layers and the lower portions of the fins define interface dipole layer barriers, portions of the capping layers operable to provide increased negative charges or increased positive charges adjacent to the fins, to reduce punch-through leakage compared to fins not having the capping layers.

9. The method of claim 8 wherein the providing the first capping layer comprises providing the first capping layer over the some of the upper portions and the lower portions of the fins disposed over at least one of an NFET region in the substrate and an PFET region in the substrate.

10. The method of claim 9 wherein the providing the second capping layer comprises providing the second capping layer over the other of the upper portions and the lower portions of the fins disposed over the other of at least one of the NFET region in the substrate and the PFET region in the substrate.

11. The method of claim 8 wherein the portion of the first capping layer defining the portion of the dipole layer interface barrier comprises a negative charge or a positive charge, and the portion of the second capping layer defining the portion of the dipole layer interface barrier comprises a positive charge or a negative charge, respectively.

12. The method of claim 8 wherein at least one of the first and second capping layer comprises an oxide.

13. The method of claim 8 wherein at least one of the first and second capping layer comprises strontium oxide, lanthanum oxide, lutetium oxide, yttrium oxide, germanium oxide, and the second capping layer comprises aluminum oxide, titanium dioxide, zirconium dioxide, hafnium oxide, or magnesium oxide.

14. The method of claim 8 further comprising forming a plurality of gates disposed over the upper portions of the fins.