Formation of metal resistor and e-fuse

• US 9,312,185 B2
• Filed: 05/06/2014
• Issued: 04/12/2016
• Est. Priority Date: 05/06/2014
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Tran, Cung, Alptekin, Emre, Sardesai, Viraj, Vega, Reinaldo
• Primary Examiner(s): Nadav, Ori
• Application Number:
  US14/270,791
• Publication Number:
  US 20150325483A1
• Time in Patent Office: 707 Days
• Field of Search: 438/210, 438/230, 438/238, 438/382, 438/586, 438/597
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/31055 the removal being a chemical etching step, e.g. dry etching etching per se H01L21/311
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823443 silicided or salicided gate conductors
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/24 with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66515 using self aligned selective metal deposition simultaneously on the gate and on source or drain
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Embodiments of present invention provide a method of forming metal resistor. The method includes forming a first and a second structure on top of a semiconductor substrate in a replacement-metal-gate process to have, respectively, a sacrificial gate and spacers adjacent to sidewalls of the sacrificial gate; covering the second structure with an etch-stop mask; replacing the sacrificial gate of the first structure with a replacement metal gate; removing the etch-stop mask to expose the sacrificial gate of the second structure; forming a silicide in the second structure as a metal resistor; and forming contacts to the silicide. In one embodiment, forming the silicide includes siliciding a top portion of the sacrificial gate of the second structure to form the metal resistor. In another embodiment, forming the silicide includes removing the sacrificial gate of the second structure to expose and silicide a channel region underneath thereof.

Claims

1. A method comprising:

providing a semiconductor substrate;

forming a group of transistor structures designated for forming transistors and at least one additional transistor structure designated for forming a metal resistor on said semiconductor substrate, wherein said additional transistor structure includes a first source/drain silicide and a second source/drain silicide, and wherein each of said first and second source/drain silicides are laterally separated from said group of transistor structures;

forming an etch-stop mask directly on top of said additional transistor structure;

with said etch-stop mask protecting said additional transistor structure, replacing sacrificial gates in said group of transistor structures to form metal gates of said transistors;

removing said etch-stop mask, after forming said metal gates, to expose said additional transistor structure;

forming a resistor silicide in a portion of said semiconductor substrate positioned in said additional transistor structure as said metal resistor, and laterally between said first and second source/drain silicides; and

forming a first contact on said first source/drain silicide and a second contact on said second source/drain silicide, wherein said first and second contacts are electrically connected to each other through said resistor silicide.

2. The method of claim 1, wherein forming said resistor silicide comprises:

removing a sacrificial gate of said additional transistor structure;

siliciding a channel region of said additional transistor structure, said channel region being previously underneath said sacrificial gate and being exposed by the removal thereof; and

covering said silicided channel region with a dielectric material.

3. The method of claim 1, further comprises, before removing said etch-stop mask:

forming a recess in a top portion of at least one of said metal gates of said transistors; and

depositing a dielectric material on top of said transistors and on top of said etch-stop mask, said dielectric material filling said recess.

4. The method of claim 3, wherein removing said etch-stop mask comprises:

applying a chemical-mechanic-polishing (CMP) process in removing said dielectric material on top of said transistor, said removing removes said etch-stop mask together with said dielectric material, exposing said additional transistor structure underneath said etch-stop mask and leaving only a dielectric cap said recess of said at least one of said metal gates.

5. The method of claim 4, wherein said dielectric material and said etch-stop mask have a significantly similar property relating to said CMP process.

6. The method of claim 4, wherein said dielectric material and said etch-stop mask are made of a same dielectric material.

7. A method comprising:

forming a first structure for a transistor and a second structure for a metal resistor on a semiconductor substrate, wherein said second structure includes a first source/drain silicide and a second source/drain silicide, and wherein said second structure is laterally separated from each of said first source/drain silicide and said second source/drain silicide;

covering said second structure with a protection mask;

replacing a sacrificial gate of said first structure with a metal gate of said transistor;

removing said protection mask, after forming said metal gate, to expose a top of said second structure;

forming a resistor silicide in a portion of said semiconductor substrate positioned in said second structure as said metal resistor, and laterally between said first and second source/drain silicides; and

forming a first contact on said first source/drain silicide and a second contact on said second source/drain silicide, wherein said first and second contacts are electrically connected to each other through said resistor silicide.

8. The method of claim 7, wherein forming said resistor silicide comprises:

removing a sacrificial gate of said second structure;

siliciding a channel region of said second structure, said channel region being exposed by the removal of said sacrificial gate; and

covering said silicided channel region with a dielectric material.

9. The method of claim 7, further comprises:

removing a top portion of said metal gate of said transistor to create a recess; and

depositing a dielectric material inside said recess, on top of said transistor, and on top of said protection mask that is on top of said second structure.

10. The method of claim 9, wherein removing said protection mask comprises:

applying a chemical-mechanic-polishing (CMP) process to remove said dielectric material on top of said protection mask and a portion of said dielectric material on top of said transistor; and

continuing said CMP process to remove said protection mask and a remaining portion of said dielectric material on top of said transistor, leaving only a dielectric cap inside said recess of said metal gate of said transistor.

11. The method of claim 10, wherein said dielectric material and said protection mask are made of a same dielectric material to have significantly similar property of said CMP process.

12. The method of claim 7, further comprising siliciding source/drain regions of said first structure and source/drain regions of said second structure.

13. A method comprising:

forming a first structure and a second structure on top of a semiconductor substrate in a replacement-metal-gate (RMG) process to have, respectively, a sacrificial gate, spacers adjacent to sidewalls of said sacrificial gate, and first and second silicided source/drain regions of at least said first structure each adjacent to a respective one of said spacers;

said first and second structures being embedded in a first dielectric layer, wherein said first and second silicided source/drain regions of said second structure are laterally separated from said first and second silicided source/drain regions of said first structure;

covering said second structure with an etch-stop mask;

replacing said sacrificial gate of said first structure with a replacement metal gate;

removing said etch-stop mask to expose said sacrificial gate of said second structure;

forming a silicide in a portion of said semiconductor substrate positioned in said second structure as a metal resistor; and

forming a first contact on said first silicided source/drain region of said second structure and a second contact on said second silicided source/drain region of said second structure, wherein said first and second contacts are electrically connected to each other through said silicide.

14. The method of claim 13, wherein forming said silicide comprises:

removing said sacrificial gate of said second structure to expose a channel region underneath thereof;

siliciding said channel region of said second structure; and

covering said silicided channel region with a dielectric material.