Method of forming horizontal gate all around structure

• US 9,312,186 B1
• Filed: 11/04/2014
• Issued: 04/12/2016
• Est. Priority Date: 11/04/2014
• Status: Active Grant

• Current Assignee: Advanced Manufacturing Innovations Incorporated
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Su, Huan-Chieh, Wang, Chien-Hsun, Lin, Chun-Hsiung, Huang, Jui-Chien, Lin, Chun-An
• Primary Examiner(s): Chaudhari, Chandra
• Application Number:
  US14/532,074
• Publication Number:
  US 20160126143A1
• Time in Patent Office: 525 Days
• Field of Search: 438/283, 438/284
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66439 with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor with an active layer made of a group 13/15 material H01L29/66469
• CPC Class Codes: H01L 29/66469 with one- or zero-dimensional channel, e.g. quantum wire field-effect transistors, in-plane gate transistors [IPG], single electron transistors [SET], Coulomb blockade transistors, striped channel transistors
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET

Abstract

This disclosure provides a horizontal structure by using a double STI recess method. The double STI recess method includes: forming a plurality of fins on the substrate; forming shallow trench isolation between the fins; performing first etch-back on the shallow trench isolation; forming source and drain regions adjacent to channels of the fins; and performing second etch-back on the shallow trench isolations to expose a lower portion of the fins as a larger process window for forming gates of the fins. Accordingly, compared to conventional methods limited by fin height from the STI, the double STI recess method provides greater fin height, which is a larger process window for HGAA nanowire formation, to easily produce multi-stack HGAA nanowires with high current density. The number of layers used in the multi-stack HGAA nanowires is not limited and may vary based on different designs.

Claims

1. A method of forming a semiconductor device having a horizontal gate all around structure on a substrate, the method comprising:

forming a plurality of fins on the substrate, each fin comprising a top channel layer, a bottom channel layer below the top channel layer, a top sacrificial layer between the top channel layer and the bottom channel layer, and a bottom sacrificial layer between the substrate and the bottom channel layer;

forming a shallow trench isolation between the fins;

etching the shallow trench isolation to expose a portion of the fins above a first level;

etching the shallow trench isolation to expose the portion of the fins above a second level which is lower than the first level; and

removing the top sacrificial layer and the bottom sacrificial layer above the second level.

2. The method of claim 1, wherein etching back the shallow trench isolation again to expose the portion of the fins above the second level lower than the first level further comprises etching back the shallow trench isolation to expose the portion of the fins above the second level lower than the first level for about 10-50 nanometers.

3. The method of claim 1, wherein etching back the shallow trench isolation material to expose the portion of the fins comprises etching back the shallow trench isolation material to expose the portion of the fins having a height less than about 50 nanometers.

4. The method of claim 1, further comprising oxidizing the top sacrificial layer and the bottom sacrificial layer.

5. The method of claim 1, wherein first etching back the shallow trench isolation further comprises etching back the shallow trench isolation to expose the top sacrificial layer of the fin.

6. The method of claim 1, wherein second etching back the shallow trench isolation further comprises etching back the shallow trench isolation to expose the bottom sacrificial layer of the fin.

7. A method of forming a semiconductor device having a horizontal gate all around structure on a substrate, the method comprising:

forming a plurality of fins on the substrate, each fin comprising a top channel layer, a bottom channel layer below the top channel layer, a top sacrificial layer between the top channel layer and the bottom channel layer, and a bottom sacrificial layer between the substrate and the bottom channel layer;

providing a shallow trench isolation between the fins;

forming poly layer over a preset portion of the fins;

forming source and drain regions adjacent to the preset portion;

forming an interlayer dielectric layer over the source and drain regions;

forming a cap layer over the interlayer dielectric layer;

removing the poly layer;

etching back the shallow trench isolation;

removing a portion of the top sacrificial layer and the bottom sacrificial layer; and

forming the gate around the top channel layer and the bottom channel layer.

8. The method of claim 7, wherein forming the cap layer over the interlayer dielectric layer further comprises:

etching back the interlayer dielectric layer;

forming a nitride layer over the poly layer and the interlayer dielectric layer;

performing CMP on the nitride layer and stopping at the poly layer; and

removing the poly layer.

9. The method of claim 8, wherein forming the nitride layer over the poly layer and the interlayer dielectric layer further comprises:

forming the nitride layer by using at least one of SiN and SiCN.

10. A method of forming a semiconductor device having a horizontal gate all around structure on a substrate, the method comprising:

forming a plurality of fins on the substrate, each fin comprising a top channel layer, a bottom channel layer below the top channel layer, a top sacrificial layer between the top channel layer and the bottom channel layer, and a bottom sacrificial layer between the substrate and the bottom channel layer;

providing a shallow trench isolation between the fins;

forming poly layer over a preset portion of the fins;

forming source and drain regions adjacent to the preset portion;

forming an interlayer dielectric layer over the source and drain regions;

removing the poly layer;

etching back the shallow trench isolation;

removing a portion of the top sacrificial layer and the bottom sacrificial layer; and

forming the gate around the top channel layer and the bottom channel layer.

11. The method of claim 10, wherein etching back the shallow trench isolation again to expose the portion of the fins above the second level lower than the first level further comprises etching back the shallow trench isolation to expose the portion of the fins above the second level lower than the first level for about 10-50 nanometers.

12. The method of claim 10, wherein providing the shallow trench isolation between the fins further comprises:

forming shallow trench isolation material between the fins; and

etching back the shallow trench isolation material to expose a portion of the fins.

13. The method of claim 10, wherein etching back the shallow trench isolation material to expose the portion of the fins comprises etching back the shallow trench isolation material to expose the portion of the fins having a height less than about 50 nanometers.

14. The method of claim 10, further comprising forming a cap layer over the interlayer dielectric layer.

15. The method of claim 10, wherein forming the cap layer over the interlayer dielectric layer further comprises:

etching back the interlayer dielectric layer;

forming a nitride layer over the poly layer and the interlayer dielectric layer;

performing CMP on the nitride layer and stopping at the poly layer; and

removing the poly layer.

16. The method of claim 15, wherein forming the nitride layer over the poly layer and the interlayer dielectric layer further comprises:

forming the nitride layer by using at least one of SiN and SiCN.

17. The method of claim 10, wherein forming the source and drain regions comprises creating recesses in the fins for the source and drain regions.

18. The method of claim 10, further comprising:

forming hard masks to protect a top of the poly layer; and

forming spacers to protect a sidewall of the poly layer.

19. The method of claim 10, wherein forming the fins on the substrate further comprises forming the fins with Si as the top channel layer and the bottom channel layer and with SiGe as the top sacrificial layer and the bottom sacrificial layer.

20. The method of claim 10, further comprising oxidizing the top sacrificial layer and the bottom sacrificial layer.