Stress relief structures in package assemblies

• US 9,312,193 B2
• Filed: 11/09/2012
• Issued: 04/12/2016
• Est. Priority Date: 11/09/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Hsien-Wei
• Primary Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US13/673,703
• Publication Number:
  US 20140131877A1
• Time in Patent Office: 1,250 Days
• Field of Search: 257/769, 257/774, 257/773, 257/775, 257/776, 257/685, 257/686, 257/723, 257/728, 257/724, 257/714, 257/620, 257/E21.214, 257/770
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/16 Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/3511 Warping

Abstract

A semiconductor package structure, comprises a substrate, a die region having one or more dies disposed on the substrate, and at least one stress relief structure disposed at one or more corners of the substrate, the at least one stress relief structure being adjacent to at least one die of the one or more dies.

Claims

1. A semiconductor package structure, comprising:

a substrate;

a solder region;

one or more dies bonded on the substrate through the solder region; and

two or more stress relief structures, each stress relief structure of the stress relief structures being formed on or bonded onto a surface of the substrate and being disposed adjacent to at least one die of the one or more dies, wherein a first stress relief structure of the two or more stress relief structures has a different shape from a second stress relief structure of the two or more stress relief structures,

wherein

upper surfaces of the stress relief structures are unconnected; and

at least one stress relief structure of the two or more stress relief structures is disposed adjacent to a corner of the at least one die, and the at least one stress relief structure comprises;

a first portion extending along a first side of the at least one die, the first side being associated with the corner of the at least one die; and

a second portion extending along a second side of the at least one die, the second side being associated with the corner of the at least one die,

wherein the two or more stress relief structures individually comprise a material selected from the group consisting of a thermally conductive material, metal, tungsten, aluminum, aluminum alloy, polysilicon, silicide, tantalum, refractory metal, copper, copper alloy, gold, gold alloy, TaN, titanium, TiN, nickel, and combinations thereof.

2. The semiconductor package structure of claim 1, wherein the stress relief structures have irregular shapes selected from the group consisting of a square, a rectangle, a triangle, a circle, an L-shape, a T-shape, a broken strip, a rectangular array, a cross, and a polygon.

3. The semiconductor package structure of claim 1, wherein the stress relief structures have random sizes, random thicknesses, and/or random orientations.

4. The semiconductor package structure of claim 1, wherein the stress relief structures comprise substantially a same material as the substrate and/or the one or more dies.

18. The semiconductor package of claim 1, further comprising an underfill between each die of the one or more dies and the substrate, wherein the at least one stress relief structure is spaced from the underfill.

19. The semiconductor package of claim 1, wherein a spacing between at least one stress relief structure of the stress relief structures and a nearest die of the one or more dies is greater than about 2 μ

m.

5. A semiconductor package structure, comprising:

a substrate;

a solder region;

a plurality of dies, with at least one die of the plurality of dies being larger than the other dies of the plurality of dies, the plurality of dies being bonded on the substrate through the solder region;

an underfill between each die of the plurality of dies and the substrate; and

two or more stress relief structures, each stress relief structure of the stress relief structures being formed on or bonded onto a surface of the substrate and being disposed adjacent to the at least one die of the plurality of dies, wherein at least a first stress relief structure of the two or more stress relief structures are spaced from each die of the plurality of dies in a direction parallel to a top surface of the substrate, and a second stress relief structure of the two or more stress relief structures is spaced from the underfill,

wherein

upper surfaces of the stress relief structures are unconnected; and

at least one stress relief structure of the two or more stress relief structures is disposed adjacent to a corner of the at least one die, and the at least one stress relief structure comprises;

a first portion extending along a first side of the at least one die, the first side being associated with the corner of the at least one die; and

a second portion extending along a second side of the at least one die, the second side being associated with the corner of the at least one die.

6. The semiconductor package structure of claim 5, wherein the stress relief structures comprise a material selected from the group consisting of a thermally conductive material, metal, tungsten, aluminum, aluminum alloy, polysilicon, silicide, tantalum, refractory metal, copper, copper alloy, gold, gold alloy, TaN, titanium, TiN, nickel, and combinations thereof.

7. The semiconductor package structure of claim 5, wherein the stress relief structures have irregular shapes selected from the group consisting of a square, a rectangle, a triangle, a circle, an L-shape, a T-shape, a broken strip, a rectangular array, a cross, and a polygon.

8. The semiconductor package structure of claim 5, wherein the stress relief structures have random sizes, random thicknesses, and/or random orientations.

9. The semiconductor package structure of claim 6, wherein the stress relief structures are bonded onto the substrate by an adhesive.

10. The semiconductor package structure of claim 9, wherein the adhesive has a thermal conductivity greater than about 10 W/m°

C.

11. The semiconductor package structure of claim 5, wherein the stress relief structures are bonded onto the substrate by an adhesive.

12. The semiconductor package structure of claim 11, wherein the adhesive has a thermal conductivity greater than about 10 W/m°

C.

13. A semiconductor package structure, comprising:

a substrate;

a solder region;

one or more dies bonded on the substrate through the solder region;

an underfill between each die of the one or more dies and the substrate; and

two or more stress relief structures, each stress relief structure of the stress relief structures being formed on or bonded onto a surface of the substrate and being disposed adjacent to at least an identified largest die of the one or more dies, wherein at least a first stress relief structure of the two or more stress relief structures is spaced from each die of the one or more dies in a direction parallel to a top surface of the substrate, and at least a second stress relief structure of the two or more stress relief structures spaced from the underfill,

wherein

upper surfaces of the stress relief structures are unconnected; and

at least one stress relief structure of the two or more stress relief structures is disposed adjacent to a corner of the identified largest die, and the at least one stress relief structure comprises;

a first portion extending along a first side of the identified largest die, the first side being associated with the corner of the identified largest die; and

a second portion extending along a second side of the identified largest die, the second side being associated with the corner of the identified largest die.

14. The semiconductor package structure of claim 13, wherein the stress relief structures comprise substantially a same material as the package substrate and/or the one or more individual dies.

15. The semiconductor package structure of claim 13, wherein the stress relief structures comprise a material comprising a thermally conductive material, metal, tungsten, aluminum, aluminum alloy, polysilicon, silicide, tantalum, refractory metal, copper, copper alloy, gold, gold alloy, TaN, titanium, TiN, nickel, or combinations thereof.

16. The semiconductor package structure of claim 13, wherein the stress relief structures are bonded onto the package substrate by an adhesive.

17. The semiconductor package structure of claim 16, wherein the adhesive has a thermal conductivity greater than about 10 W/m°

C.