Method for producing display panel, and display panel

• US 9,312,283 B2
• Filed: 03/18/2014
• Issued: 04/12/2016
• Est. Priority Date: 11/16/2011
• Status: Active Grant

• Current Assignee: JDI Design and Development GK
• Original Assignee: JOLED Inc.
• Inventors: Nanai, Norishige, Ukeda, Takaaki, Miyamoto, Akihito
• Primary Examiner(s): Diaz, Jose R
• Application Number:
  US14/217,817
• Publication Number:
  US 20140197417A1
• Time in Patent Office: 756 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 27/1292 using liquid deposition, e.g. printing
• CPC Class Codes: H10K 59/1201 Manufacture or treatment
• CPC Class Codes: H10K 59/122 Pixel-defining structures or layers, e.g. banks
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements

Abstract

In a method for producing a display panel, a base substrate having an upper surface on which an electrode is located is prepared. A first layer having a first opening overlapping with the electrode in plan-view is formed on the base substrate. A second layer having a second opening overlapping with the first opening in plan-view is formed on the first layer. The second opening has a smaller area than the first opening in plan-view. A wiring layer is formed in the first opening and the second opening, in contact with the electrode. The second layer includes a portion located on an upper surface of the first layer and a portion located in the first opening. The portion of the second layer located in the first opening covers an internal side surface of the first layer located around the first opening.

Claims

1. A transistor array comprising:

a base substrate;

a gate electrode located on an upper surface of the base substrate;

a gate insulating film located on the base substrate and having a first opening therein at a position overlapping with the gate electrode in plan-view;

a bank layer located on the gate insulating film and having a second opening therein at a position overlapping with the first opening in plan-view, the second opening having a smaller area than the first opening in plan-view; and

a wiring layer located in the first opening and the second opening, in contact with the gate electrode, wherein

the bank layer includes a portion located on an upper surface of the gate insulating film and a portion located in the first opening, and

the portion of the bank layer located in the first opening covers an internal side surface of the gate insulating film located around the first opening.

2. The transistor array of claim 1, wherein

the bank layer has a third opening therein at a different position to the second opening, the third opening being for formation of a functional material layer including at least a semiconductor layer.

3. The transistor array of claim 1, wherein

the wiring layer is a source electrode or a drain electrode.

4. The transistor array of claim 1, wherein

the bank layer has a third opening,

a semiconductor layer is located in the third opening, and

the wiring layer is further located in the third opening, in further contact with a top surface of the semiconductor layer.

16. The method for producing a display panel of claim 1, wherein

the first opening has a smaller area than the gate electrode in plan-view, and

a lower surface of the portion of the bank layer in the first opening is in contact with an upper surface of the gate electrode around an entire perimeter of the first opening in plan-view.

17. The method for producing a display panel of claim 1, wherein

in the forming of the bank layer, the bank layer is formed such that the bank layer has a third opening therein at a different position to the second opening, the third opening being for formation of a functional material layer including at least a semiconductor layer.

18. The method for producing a display panel of claim 1, wherein

the wiring layer is a source electrode or a drain electrode.

19. The method for producing a display panel of claim 1, wherein

the bank layer has a greater tolerance than the gate insulating film against a gas or liquid chemical used after the forming of the bank layer.

20. The method for producing a display panel of claim 1, wherein

the bank layer has a third opening,

a semiconductor layer is formed in the third opening, and

the wiring layer is further formed in the third opening such that the wiring layer is further in contact with a top surface of the semiconductor layer.

5. A display panel comprising:

a base substrate;

a gate electrode located on an upper surface of the base substrate;

a gate insulating film located on the base substrate and having a first opening therein at a position overlapping with the gate electrode in plan-view;

a bank layer located on the gate insulating film and having a second opening therein at a position overlapping with the first opening in plan-view, the second opening having a smaller area than the first opening in plan-view; and

a wiring layer located in the first opening and the second opening, in contact with the gate electrode, wherein

the bank layer includes a portion located on an upper surface of the gate insulating film and a portion located in the first opening, and

the portion of the bank layer located in the first opening covers an internal side surface of the gate insulating film located around the first opening.

6. The display panel of claim 5, wherein

the bank layer has a third opening therein at a different position to the second opening, the third opening being for formation of a functional material layer including at least a semiconductor layer.

7. The display panel of claim 5, wherein

the wiring layer is a source electrode or a drain electrode.

8. The display panel of claim 5, wherein

the bank layer has a third opening,

a semiconductor layer is located in the third opening, and

the wiring layer is further located in the third opening, in further contact with a top surface of the semiconductor layer.

9. A method for producing a transistor array, comprising:

preparing a base substrate having an upper surface on which a gate electrode is located;

forming a gate insulating film on the base substrate such that the gate insulating film has a first opening therein at a position overlapping with the gate electrode in plan-view;

forming a bank layer on the gate insulating film such that the bank layer has a second opening therein at a position overlapping with the first opening in plan-view, the second opening having a smaller area than the first opening in plan-view; and

forming a wiring layer in the first opening and the second opening such that the wiring layer is in contact with the gate electrode, wherein

the bank layer includes a portion located on an upper surface of the gate insulating film and a portion located in the first opening, and

the portion of the bank layer located in the first opening covers an internal side surface of the gate insulating film located around the first opening.

10. The method for producing a transistor array of claim 9, wherein

the first opening has a smaller area than the gate electrode in plan-view, and

a lower surface of the portion of the bank layer in the first opening is in contact with an upper surface of the gate electrode around an entire perimeter of the first opening in plan-view.

11. The method for producing a transistor array of claim 9, wherein

in the forming of the bank layer, the bank layer is formed such that the bank layer has a third opening therein at a different position to the second opening, the third opening being for formation of a functional material layer including at least a semiconductor layer.

12. The method for producing a transistor array of claim 9, wherein

the wiring layer is a source electrode or a drain electrode.

13. The method for producing a transistor array of claim 9, wherein

the bank layer has a greater tolerance than the gate insulating film against a gas or liquid chemical used after the forming of the bank layer.

14. The method for producing a transistor array of claim 9, wherein

the bank layer has a third opening,

a semiconductor layer is formed in the third opening, and

the wiring layer is further formed in the third opening such that the wiring layer is further in contact with a top surface of the semiconductor layer.

15. A method for producing a display panel, comprising:

preparing a base substrate having an upper surface on which a gate electrode is located;

forming a gate insulating film on the base substrate such that the gate insulating film has a first opening therein at a position overlapping with the gate electrode in plan-view;

forming a bank layer on the gate insulating film such that the bank layer has a second opening therein at a position overlapping with the first opening in plan-view, the second opening having a smaller area than the first opening in plan-view; and

forming a wiring layer in the first opening and the second opening such that the wiring layer is in contact with the gate electrode, wherein

the bank layer includes a portion located on an upper surface of the gate insulating film and a portion located in the first opening, and

the portion of the bank layer located in the first opening covers an internal side surface of the gate insulating film located around the first opening.