FinFET with epitaxial source and drain regions and dielectric isolated channel region

• US 9,312,360 B2
• Filed: 05/01/2014
• Issued: 04/12/2016
• Est. Priority Date: 05/01/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Divakaruni, Ramachandra, Khakifirooz, Ali, Reznicek, Alexander, Seo, Soon-Cheon
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): SINGAL, ANKUSH K
• Application Number:
  US14/267,573
• Publication Number:
  US 20150318377A1
• Time in Patent Office: 712 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.

Claims

1. A structure comprising:

a pedestal of an insulating material present over at least one layer of a semiconductor material that includes a punch through barrier layer and a semiconductor substrate, wherein the punch-through layer is present between the pedestal of the insulating material and the semiconductor substrate;

at least one fin structure in contact with the pedestal of the insulating material;

source and drain region structures on opposing sides of the at least one fin structure, at least one of the source and drain region structures comprising at least two epitaxial material layers, wherein a first epitaxial material layer of the at least two epitaxial layers is in contact with the punch through barrier layer of the at least one layer of semiconductor material, and a second epitaxial material layer of the at least two epitaxial layers is in contact with the at least one fin structure, the first epitaxial material layer being separated from the at least one fin structure by the second epitaxial material layer; and

a gate structure present on the at least one fin structure.

2. The structure according to claim 1, wherein the at least one fin structure is a channel region, and an interface between the second epitaxial material layer of the source and drain region structures and the channel region is substantially free of defects.

3. The structure according to claim 1, wherein the punch through layer is a doped portion of the substrate.

4. The structure according to claim 1, wherein the punch-through layer is doped to a conductivity type that is opposite a conductivity type of the source and drain region structures.

5. The structure according to claim 1, wherein the second epitaxial layer is in contact with the punch-through layer.

6. The structure according to claim 1, wherein a gate sidewall spacer is present on the gate structure, wherein a sidewall of the fin structure is aligned with an outer sidewall of the gate sidewall spacer, the first epitaxial material layer having a vertical portion in contact with the sidewall of the fin structure and a horizontal portion on an upper surface of the second epitaxial material layer.

7. The structure according to claim 5, wherein the first epitaxial material layer has a crystalline structure that is aligned with a crystalline structure of the punch-through layer, and the second epitaxial material layer has a crystalline structure that is aligned with a crystal structure of the sidewall of the at least one fin structure.

8. The structure according to claim 1, wherein the structure is a FinFET semiconductor device.

9. A method comprising:

providing at least one fin structure over a stacked structure of an insulator layer that is present over at least one semiconductor layer;

providing a gate structure on a channel region portion of the at least one fin structure;

removing exposed portions of the at least one fin structure;

forming a sacrificial spacer on a sidewall of the gate structure;

removing exposed portions of the insulator layer to provide a pedestal of insulating material exposing a portion of at least one semiconductor layer;

forming a first epitaxial material layer on the portion of the at least one semiconductor layer exposed by removing the exposed portions of the insulator layer, the first epitaxial material layer contacting the sacrificial spacer;

removing the sacrificial spacer; and

forming a second epitaxial material layer in a space provided by said removing of the sacrificial spacer, the second epitaxial material layer contacting a sidewall of the at least one fin structure, wherein the first and second epitaxial material layers provide source and drain regions on opposing sides of the channel region portion of the at least one fin structure.

10. The method according to claim 9 further comprising forming a gate sidewall spacer directly on the sidewall of the gate structure prior to the removing of the exposed portions of the insulator layer, wherein said forming the sacrificial spacer over the sidewall of the gate structure comprises forming the sacrificial spacer directly on the gate sidewall spacer.

11. The method according to claim 9, wherein the at least one semiconductor layer comprises a punch-through layer and a semiconductor substrate, wherein the punch-through layer is present between the insulating layer and the semiconductor substrate.

12. The method according to claim 11, wherein the punch-through layer is a doped layer with a dopant opposite to a dopant that dictates the conductivity type of the source and drain regions.

13. The method according to claim 9, wherein the second epitaxial material layer contacts the pedestal of insulating material and does not contact the at least one semiconductor layer.

14. The method according to claim 9, wherein the second epitaxial material layer separates the first epitaxial material layer from contacting the at least one fin structure.

15. The method according to claim 9, wherein the sacrificial spacer that is present on the sidewall of the gate structure has a base that is in contact with the pedestal of insulting material.

16. The method according to claim 9, wherein the first epitaxial material layer is epitaxially grown from a surface of the at least one semiconductor layer exposed by removing the exposed portions of the insulator layer.

17. The method according to claim 9, wherien the second epitaxial material layer is epitaxially grown from a surface of the sidewall of the at least one fin structure and a surface of the first epitaxial material layer.

18. The method according to claim 9, wherein an interface between the first epitaxial layer of the source and drain region structures and the channel region is substantially free of defects.

19. The method according to claim 9, wherein providing the gate structure on the channel region portion of the at least one fin structure comprises:

forming a sacrificial gate structure on the channel region portion of the at least one fin structure prior to forming the source and drain regions on opposing sides of the channel region portion of the at least one fin structure; and

replacing the sacrificial gate structure with a functional gate structure after forming the source and drain regions on opposing sides of the channel region portion of the at least one fin structure.